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TMS320F28388D: How to boot CPU2 and CM

Guru 13885 points

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Hi,

F28377D load CPU2 flash kernel to GS RAM, then use IPC_BRANCH call command so that CPU2 start executing code from the entry point of GS RAM.

Now my customer is using F28388D.

the IPC boot commands are different and I don't see IPC branch command(to GS RAM) in F28388D TRM.

  

(1) Can I use the F28388D IPC command to achieve the boot CPU2 and CM ?

 

(2) I think one solution is to use "IPC Message Copy to RAM Boot" instead of (1) .

  However, Message RAM has only 2KB, which is not enough.

  Is there any solution?

  

Thanks,

Koki

  • Koki,

    In F28377D, you have boot to RAM (M0RAM) for CPU2 (with entry point at 0x0). It doesn't have the option of boot to GSRAM.

    In F28388D.CPU2, you have boot to M0RAM (with entry point 0x0). Please check TRM Table 5-21. CPU1TOCPU2IPCBOOTMODE & Table 5-26. Entry Point Addresses for CPU2 for more details.

    In F28388D.CM, you have boot to S0RAM (with entry point 0x2000 0800). Please check TRM Table 5-22. CPU1TOCMIPCBOOTMODE & Table 5-27. Entry Point Addresses for CM for more details 

    Regards,

    Manoj

  • Hi, Manoj

    How do I specifically configure ?

    Thanks,

    Koki

  • Koki,

    In CPU1 code, you can execute the below function to boot to M0RAM for CPU2

    Device_bootCPU2(BOOTMODE_BOOT_TO_M0RAM);

    Refer to <C2000Ware>\driverlib\f2838x\examples\c28x_dual\ipc\ipc_ex2_msgqueue_c28x1 example code

    In CPU1 code, you can execute the below function to boot to S0RAM for CM

    Device_bootCM(BOOTMODE_BOOT_TO_S0RAM);

    Refer to <C2000Ware>\driverlib\f2838x\examples\c28x_cm\ipc\ipc_ex2_msgqueue_c28x1 example code

    Regards,

    Manoj

  • Hi, Manoj

      However, Message RAM has only 2KB, which is not enough.

    ■M0RAM  SIZE=1K    ■S0RAM  SIZE=16K

    [Q1]  Is the CPU2 code limited to 1KB because of M0RAM ? If so, the citation problem cannot be resolved.

    [Q2] Do "code of CPU2 and CM" place M0RAM and S0RAM by rewrite the linker file ? 

    Regards,

    Koki


  • Koki,

    Essentially F28388D shouldn't be any different from F28377D with respect to BOOT to RAM option.Like I mentioned in earlier message, both F28377D and F28388D have boot to RAM (with entry point at 0x0). Please try to understand how this was addressed from your side when using F28377D.

    CPU2 code is not limited to M0RAM. Entry point just means that when CPU2 branches from bootrom to RAM it starts executing code from address 0x0 of M0RAM. You still have whole CPU2 memory space (all RAMs in CPU2 available to use) for your CPU2 flash kernel usage. You can have function in M0RAM which can branch to other RAM locations just like any application software.

    Regards,

    Manoj

  • Hi, Manoj

    I'm sorry for lack of understanding.

    I understand that CPU2 and CM can use their own RAM to execute more than 2KB of code.

    If I run CPU2, CM on M0RAM and S0RAM, what are the specific steps I need to run?

    Ex) put the code in M0RAM with a linker file. ..

    Thanks,

    Koki

  • Koki,

    Have you reviewed the IPC example code I have mentioned in earlier post? Understanding the example provided will provide pointer on how you need to develop your CPU2 / CM application code. The linker command code snippets found below is available in 2838x_RAM_lnk_cpu2.cmd. Please ensure you don't change the below lines of code in your application code for CPU2.

    From : CPU2 linker command file

       /* BEGIN is used for the "boot to SARAM" bootloader mode   */
       BEGIN            : origin = 0x000000, length = 0x000002

       codestart        : > BEGIN

    Regards,

    Manoj