TMS570LS3137 Watchdog Timer Expire Reset

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Thanks,

Jay

Pritesh,

The selection between NMI and RESET is done using the RTIWWDRXNCTRL as explain below.

The DWWD NMI is connected to ESM Group 2 bit 24.

ESM group2 always generate NMI when the corresponding channel is active.

If a DWWD NMI is active, the bit 24 of ESMSR2 will be set (Status)

For the CPU to react on NMI, the F bit is CPSR as to be cleared.
Out of reset the CPU is IRQ and NMI disable. Once NMI are enable, they cannot be disable anymore by software. Only a CPU Reset will disable NMI.

Hi Jean,

Thank you for the prompt reply. Your answer is built with the assumption of using the Digital Windowed Watchdog(DWWD) Mechanism.

But what is the control procedure of the timeout expiry of the DWD? Or is there no such concept at all in this case? If so, then the text in the Reference manual should be modified. 

Regards,

Pritesh

Pritesh,

I'm not sure I understand your question but I will try to explain with my word the difference between DWD and DWWD.

Out of reset, the DWD or DWWD is disable. Once it is enable it will stay enable until a device reset.
The DWD runs out of RTI1 Clock that is used to decrement a 25bits counter. The default value for this down counter is 0x1FFFFFF.
This default value can be changed via Digital Watchdog Preload Register (RTIDWDPRLD) [offset = 94h]. This register is a 12 bits register.
The time out will be:

Time Expitation = (DWDPRLD+1) x 213 / RTICLK1
where: DWDPRLD = 0...4095

The preload value has to be set BEFORE the DWD is enable.

To enable the DWD, Digital Watchdog Control Register (RTIDWDCTRL) [offset = 90h] has to be used.
Writing 0xA98559DA to RTIDWDCTRL enable the DWD. The DWD will stay enable and will use the RTIDWDPRLD preload value until the next device reset.

For DWD, at anytime during the down count, the key sequence can be written to DWD to reload the counter with the preload value and avoid RESET or NMI.
RTI Watchdog Key Register (RTIDWDKEY) [offset = 9Ch] has to be used to write the key sequence.
A write of E51Ah followed by A35Ch in two separate write operations defines the key sequence and reloads the DWD with the preload value. Writing any other value causes a reset or NMI.

For DWWD, the key sequence has to be written within a specific time window.
The DWWD uses the Digital Watchdog (DWD) pre-load register (RTIDWDPRLD) setting to define the end-time of the window.
The start-time of the window is defined by a window size configuration register Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h].
Any attempt to service the watchdog outside this time window, or a failure to service the watchdog in this time window, will cause the watchdog to generate either a reset or a NMI to the CPU.

All these information are available in the Technical Reference Manual available at: http://www.ti.com/lit/ug/spnu499a/spnu499a.pdf

Please let me know if I've clarify and answer your question.

Hi Jean,

Thank you once again for your reply. My doubt is something different. 

How do I set the Reaction of the Digital Watchdog Timer? That is, how do I set the action(either RESET or NMI) after the Timer expires. As far as I saw in the manual,

there is a section 13.3.33 in SPNA499A which explains this for the DWWD (RTIWWDRXNCTRL register). 

But in the sections specific to DWD i.e. Sections 13.3.28, 13.3.29, 13.3.30, 13.3.31,13.3.32,  I did not find a description about how to set the reaction on expiry of the DWD.

Maybe I am missing something? Or the reaction is controlled by the RTIWWDRXNCTRL register for the DWD also?

Regards,

Pritesh

HI Jean,

Yes, that puts to rest all my doubts. Thank you. The problem was due to the convention of nomenclature of the registers.

Regards,

Pritesh