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Original question:

TMS570LS3137 with RMII

TMS570LS3137: How Can i get into RMII mode using tms570ls3137 ?

Jhon zhu
Intellectual 370 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN, DP83640

I configured the pin as fallowing :

pinMuxReg->PINMMR0 = PINMUX_BALL_C3_I2C_SCL | PINMUX_BALL_B2_I2C_SDA;

pinMuxReg->PINMMR1 = PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_EMIF_DATA_4 | PINMUX_BALL_F5_EMIF_DATA_5;

pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_EMIF_DATA_6 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;

pinMuxReg->PINMMR3 = PINMUX_BALL_K5_EMIF_DATA_7 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_EMIF_DATA_8;

pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_EMIF_DATA_9 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;

pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_EMIF_DATA_10;

pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_EMIF_DATA_12;

pinMuxReg->PINMMR7 = PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_V5_MDCLK | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_EMIF_DATA_14;

pinMuxReg->PINMMR8 = PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_MDIO | PINMUX_BALL_N1_MIBSPI1NCS_4 | PINMUX_BALL_R8_EMIF_DATA_15;

pinMuxReg->PINMMR9 = ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NCS_5 | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;

pinMuxReg->PINMMR10 = PINMUX_BALL_N19_RMII_RX_ER | PINMUX_BALL_N15_EMIF_DATA_3 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_EMIF_DATA_2;

pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_RMII_RXD_0;

pinMuxReg->PINMMR12 = PINMUX_BALL_A14_RMII_RXD_1 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;

pinMuxReg->PINMMR13 = PINMUX_BALL_J18_RMII_TXD_0 | PINMUX_BALL_J19_RMII_TXD_1 | PINMUX_BALL_H19_RMII_TXEN | PINMUX_BALL_R2_MIBSPI1NCS_0;

pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_RMII_REFCLK | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;

pinMuxReg->PINMMR15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;

pinMuxReg->PINMMR16 = PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_EMIF_nOE;

pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_EMIF_nDQM_1 | PINMUX_BALL_B4_RMII_CRS_DV | PINMUX_BALL_E9_EMIF_ADDR_5;

pinMuxReg->PINMMR18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;

pinMuxReg->PINMMR19 = PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;

pinMuxReg->PINMMR20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_HET1_17 | PINMUX_BALL_C9_EMIF_ADDR_11;

pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;

pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_EMIF_ADDR_2;

pinMuxReg->PINMMR23 = ((~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U) | PINMUX_BALL_C6_EMIF_ADDR_8;

pinMuxReg->PINMMR24 = ((~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U);

/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
pinMuxReg->PINMMR25 = ((~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U);

/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
pinMuxReg->PINMMR26 = ((~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U) | PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;

pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;

pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;

pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NCS_1;

PINMUX_GATE_EMIF_CLK_ENABLE(ON);
PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
PINMUX_ALT_ADC_TRIGGER_SELECT(1);
PINMUX_ETHERNET_SELECT(RMII);

/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
PINMUX_SET(0,A5,GIOA_0);
PINMUX_SET(18,A11,HET1_14);
PINMUX_SET(3,B3,HET1_22);
PINMUX_SET(1,C2,GIOA_1);
PINMUX_SET(21,K2,GIOB_1);
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
PINMUX_SET(0,W10,GIOB_3);


we are using an 50M CLK as an input for ref_clk and the phy is linked as fallowing:

Have I already in the RMII mode ?

But the  thread i see "We *should* be able to add a pullup resistor to a DNP location on the HDK and make it work in RMII mode. "

Is that means  we should pullup some pin of tms570ls3137  like GMII_SEL or anything else?(Value of pinMuxReg->PINMMR29 is 0x01000002)

My problem is I can read and write regs in PHY with MDIO,

I can send data to the RMII(I can see the signal on the rmii_tx0 rmii_tx1 pin), I got the tx interrupt 

But I can not receive any data from RMII (I can see the signal on the rmii_rx0 rmii_rx1 pin), I got no rx interrupt

It seems the signal can meets the requirement of tms570ls3137.

When enable the emac loopback option I got tx and rx interrupt.

Is it because I'm not in the RMII mode?

Any other point  I can check for this issue? My project is generated by HALCOGEN 

Thanks anyone HELP?

  • 0
    TI__Mastermind 21425 points
    Hello,
    I have addressed you question but the answer bay delay because 27th of May is Holiday in USA.

    Best regards,
    Miro
  • 0 in reply to Miro
    Intellectual 370 points
    Got it! Expecting your reply !
  • 0 in reply to Jhon zhu
    TI__Guru**** 198766 points
    Hi Jhon,

    Does RMII mode require both XT1 and XT2 clock input? XT2 is 50MHz reference clock input for RMII mode. I think XT1 is 25MHz clock input for MII mode.

    Can we have the HALCOGEN configuration file for pinmux?
  • 0 in reply to QJ Wang
    Intellectual 370 points

    Does RMII mode require both XT1 and XT2 clock input?

    No, XT1 is the clock  inputs to DM9162 which is supplied by an OSC , XT2 is used as ref_clk to TMS570LS3137. Both of them are 50MHz.

    Here we found DM9162 output a weak 50MHz signal, so now we cut the xt2 pin and link  the ref_clk to the OSC which is also supply for XT1.

    as dm9162 shows in it's datasheet 

    XT2 is 50MHz reference clock input for RMII mode. I think XT1 is 25MHz clock input for MII mode.

    This is my pinmux.c

    3323.pinmux.c

  • 0 in reply to QJ Wang
    Intellectual 370 points
    Hi wang ,
    still waiting for your reply.

    Thanks
  • 0 in reply to QJ Wang
    Intellectual 370 points

    Hi  QJ,

     I link my PHY to a on board switch, and link my PC to the switch too.

      I read the stat of the Network Statistics Registers, It shows that a lot of frame fragments got received! the reg Receive Frame Fragments Register goes to a big number.

    So I enabled register EMAC_RXMBPENABLE  21, 22, 23,24 bit RXCMFEN, RXCSFEN, RXCEFEN, RXCAFEN, and I get into the EMACCore0RxIsr 

    I print the data in the curr_bd->bufptr it  come out like this : ff ff 08 06 00 01 08 00 c0 a8 01 01 00 00 00 00 

    It is an ARP ECHO packet, the packet PC send is like this: 

    It seems like I lost some of bytes .

    Can you tell why i got this, is the hardware signal problem make my reception failed?

    thanks and best regards !

  • 0 in reply to Jhon zhu
    TI__Guru**** 198766 points
    Hi Jhon,

    The PHY datasheet says that if XT1 or XT2 is used for clock input (25MHz for MII, 50MHz for RMII), another pin should be left unconnected. You should not use the second XT pin for other purpose.

    Using OSC 50MHz output for MCU RMII_MHz_50_CLK is OK.

    Can you please post your halcogen configuration file (*.hcg)? Using pinmux.c to check the pinmux configuration is not a good way for me.
  • 0 in reply to QJ Wang
    Intellectual 370 points

    Hi QJ Wang,

           We had disconnected the xt2, connected OSC to the REF_CLK as you told us, but I it still not work.

           And I found the tx signal performs a little abnormal! We sent a arp packet, Instead performs 7 0x55(Preamble),1 0x5D(SFD),Destination MAC address and so on , the performs about 30 0x55 and several 0x5D as shown below.

    The red line is TX0, green line is TX1 blue line is refclk.

    In our another board using stm32 the PHY is linked as schematic diagram show has worked well. And we test the tx signal they sent 7 0x55 and 1 0x5D.

       In the receive side, the PHY can performs 6 0x55(Preamble),1 0x5D(SFD),Destination MAC address and so on . But I can only read some fragment, it seems when we read 6 bytes we lost 10 bytes.

       In out another board using stm32, the PHY can performs 6 0x55(Preamble),1 0x5D(SFD),Destination MAC address and so on, we can receive the whole packet.

       It seems like we had a little mistake on our MAC configuration, I read the RTM there are few register saying about this, MAC Configuration Register (MACCONFIG) 0~7 bit MACCFIG. But it leaves nothing but one word “MAC configuration value”. Nowhere I can find what does it mean, nether the datasheet nor the e2e.

       Have you test the TMS570LS3137 with RMII before ? I bound a lot of issue in the software.

    1. The halcogen never configure the MDIO Pin whenever you select MII or not or select the pin manually.
    2. The LWIP never set RMII speed(this issue has been found early in 2016).
    3. Dp83640LinkStatusGet() the linkStatus should be uint32 instead uint16.

      By the way here is my hcg file 

    Have I already in the RMII mode ? what else I can do with this issue?

    I really hope you can help me with this!

    Thanks and regards

  • 0 in reply to Jhon zhu
    TI__Guru**** 198766 points

    Hi Zhu,

    The hcg file you attached doesn't have your configuration: all the modules are selected, but no pinmux is check. 

  • 0 in reply to QJ Wang
    TI__Guru**** 198766 points

    Hi,

    For DP83640 PHY, the RX_DV pin has to be pulled HIGH to enable RMII mode. I am not sure for the PHY you used.

    TMS570 supports both the MII and the RMII interfaces. Only one of these two interfaces can be used at a time. A separate control register in the I/O Multiplexing Module (IOMM) allows the application to indicate the actual interface being used. This is the bit 24 of the PINMMR160 control register. This bit is set by default and selects the RMII interface

  • 0 in reply to QJ Wang
    Intellectual 370 points

    Hi Wang,

         I don't know why I open .hcg file without .dil file all the modules are selected. 

        Here I package the .hcg and .dil file. On my another PC the project looks good with .dil file!

    Thanks & Regards,2728.HALCoGen-TMS570LS31x.rar

  • 0 in reply to QJ Wang
    Intellectual 370 points

    Hi,

    For DM9162 PHY, the COL/RMII pin has been pulled HIGH to enable RMII mode. I'm quite sure the PHY is already in the RMII mode.

     Bit 24 of the PINMMR160 control register?

    I don't think there is a PINMMR160 

    Did you mean the bit 24 of the PINMMR29 ?

    It has been selected for RMII mode!

    Thanks & Regards.

  • 0 in reply to Jhon zhu
    TI__Guru**** 198766 points

    Hello Jhon,

    The pinmux is not configured properly. There are 8 conflicts in your selections.

    The last col shows the if there is conflict. Please correct the pinmux and try again:

  • 0 in reply to QJ Wang
    Intellectual 370 points

    Hi wang,

         When I found there is MDIO pin can not select by Halcogen ,I do the most of pin configure manually.

         The conflicts is not exist in my code, and you can check it by my first post.

    Thanks & regards

  • 0 in reply to QJ Wang
    Intellectual 370 points

    Hi wang,

        Can u tell why my tx pin sent so much 0x55?

        Is it normal? 

        What does "MAC Configuration Register (MACCONFIG) 0~7 bit MACCFIG" exactly mean or Where can I found what it mean?

  • 0 in reply to Jhon zhu
    TI__Guru**** 198766 points

    Hi Jhon,

    It is configuration number of the design. This register is read-only register, and it is not configurable.

    In pinmux tab, you MII or RMII is checked, the 2 MDIO signals are not checked automatically, you have to select them manually. This is a known issue, and will be addressed in next release.

    You are right, it is PINMMR29.

    I don't know if 0x55 is normal or not in your setup.