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Original question:

HalCoGen TMS570LS3137HDK self test bug

TMS570LS3137: Single bit ECC exception handling

sreenivasan m
Genius 3705 points
Part Number: TMS570LS3137

Hi Team,

Could see in sys_selftest.c file, under CheckRAM ECC method, after injecting single bit ecc error status, we are check the status bit (bit 0) in RAMERRSTATUS register and if set, will clear ESM status registers.

But, could see that we also need to clear other bit fields in RAMERRSTATUS register. Can you please check why it is not getting clearing the source of error during self test? Also, could see if we can perform read and write operation of the same register (RAMERRSTATUS) during exception handling, it will clear the pending interrupts. Is there is an example or steps documented to perform set of actions when single bit ECC TCRAM or Flash error happens?

  • 0
    Genius 3705 points

    Hi Again,

    Does WADDR_PAR_FAIL and RADDR_PAR_FAIL indicate single or double parity errors. To be more specific, will it be correctable or correctable ecc errors?

  • 0 in reply to sreenivasan m
    TI__Mastermind 21425 points

    Hello,

    Bit 0 of RAMERRSTATUS register indicates single-bit error detected by SECDED logic. When checkRAMECC is called such an error is expected and then the flag for single bit error in RAMERRSTATUS and ESM Group 1 Channels 26 ( RAM even bank (B0TCM) - correctable error ) and 28 ( RAM odd bank (B1TCM) - correctable error ) are cleared.

    Another safety feature implemented in TMS570LS3137 MCU is Support for Cortex-R4F CPU's Address and Control Bus Parity Checking. The Cortex-R4F CPU calculates a single parity-bit for the TCRAM address and control signals. The TCRAM interface module also computes this parity bit based on the CPU's address bus and control signals. The computed parity bit is compared against the parity bit received from the CPU. A mismatch is signaled as an Address Parity Failure to the Error Signaling Module (ESM) group2 channel 10 or 12. There is a separate address parity failure error channel for B0TCM and B1TCM. RADDR_PAR_FAIL and the WADDR_PAR_FAIL status flags in the RAMERRSTATUS register indicats the type of the access ( read/write ) that ffailed in parity check. The parity bit is only suitable for detecting errors. it cannot correct any errors, as there is no way to determine which particular bit is corrupted. This mechanism enables the detection of single bit errors. The checkRAMECC function does not test Parity Failure and if you clear appropriate bits then real error may be missed.

    ADDR_COMP_LOGIC_FAIL and ADDR_DEC_FAIL bits are to indicate errors on Redundant address decode and again this is not part of checkRAMECC function.

    You can find information about steps for Introducing An Error Into RAM ECC in this app note:
    http://www.ti.com.cn/cn/lit/an/spna126/spna126.pdf

    Best regards,
    Miro

  • 0 in reply to Miro
    Genius 3705 points

    Thanks, for ADDR_COMP_LOGC_FAIL and ADD_DEC_FAIL, we will be getting ESM2 group2 channel 6 or 8 is signalled. Please confirm.

  • 0 in reply to sreenivasan m
    Genius 3705 points

    Also, let me know how to test these scenarios?

  • 0
    Genius 3705 points

    Part Number: TMS570LS3137

    Hi Team,

    This is continuation of the case https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/810075. Can you please help in answering below questions:

    For ADDR_COMP_LOGC_FAIL and ADD_DEC_FAIL, we will be getting ESM2 group2 channel 6 or 8 is signalled. Please confirm and how to test it by reproducing the scenario?

  • 0 in reply to sreenivasan m
    TI__Mastermind 21425 points

    Hello,

    When decode errors  are detected ESM2 Group2 channel 6 and channel 8 are the channels where this will be flagged.

    From sys_selftest.c, checkRAMUERRTest() is to test the redundant address decode and compare logic for the SRAM.

    Best regards,

    Miro