art Number: TMS570LS3137
Hi ,
On my Board NOR FLASH device is connected as Figure 17.8b in TMS570LS31x/21x TRM and the EMIF registers are set to:
Actually, I am seeing two writings WE# instead of just one.
For instance, when I write a simple 16 bits word at address "0006" of external asynchronous memory region (0x60000000),
The TMS first writes an other 16 bits word at address "0005" with WE#, and then it writes the good 16 bits word at address "0006" with another WE#.
So it seems that the TMS automatically writes an other word at the address next to the good one and then writes correctly at the good address.
Do you think that this extra writing at the address next to the good one could be caused by an other setting in HalCoGen ? Or even a setting in Code Composer Studio ?
The Address signal generated to NOR FLASH A1 and NOR FLASH A0 (EMIF_BA1 and EMIF_A0 lines of TMS570LS3137) are not correct .
OSCILLOSCOPE plots of EMIF A0 to A15 ( Address line EMIF BA1 to EMIF A14 ) and I found an deviation from specification on TMS570LS3137
The Address signal generated on A1 and A0 are not correct.
Following Oscilloscope plot shows execution of sending same values for 3 lower nibbles and reading the A0 & A1 that should follow A4 & A5 that should follow A8& A9 .
Attached my test project that I am using to perform test , with adding errata fix of line in main systemREG1->GPREG1 |= 0x80000000;
Error found wrong NOR FLASH Address A0 and A1 toggling for *( (uint16_t *)base_addr + 0x000C ) = 0x00AA; expected 1100 binary
A2 is 1
A1 is 1
A0 is 1 Wrong bit set
BA1 is 0
Error found wrong NOR FLASH Address A0 and A1 toggling for *( (uint16_t *)base_addr + 0x0005 ) = 0x00AA; expected 0101 binary
A2 is 0
A1 is 1
A0 is 1 Wrong bit set
BA1 is 0 Wrong Bit Reset
working as ok for *( (uint16_t *)base_addr + 0x000A ) = 0x00AA;
A2 is 1
A1 is 0
A0 is 1
BA1 is 0
working as ok for *( (uint16_t *)base_addr + 0x000F ) = 0x00AA;
A2 is 1
A1 is 0
A0 is 1
BA1 is 0
On the HALCOGEN PINMUX there L17 EMIF_nCS2 is not populated . K17 EMIF_nCS3 and M17 EMIF_nCS4 are populated .
Should the HalCoGen not generate correct code for the NOR EMIF addr signals connected to NOR flash?
EMIF_BA[1] is connected to NOR FLASH memory A[0], and the EMIF A[x] is connected to memory A[x+1]. as shown in following schematic .
Similar problem was mentioned in following thread with no solution
https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/284785?EMIF-16-bit-async-write-generates-multiple-writes
2nd thread
https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/788623?TMS570LS3137-EMIF-Asynchronous-Timing-unable-to-Write-Read-device-properly
Following suggestions are implemented
1. Please make your pinmux is configured correctly.
2. For memory interface, the EMIF address pin EMIF_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when interfacing to a 16-bit asynchronous device, the EMIF_BA[1] pin provide the least-significant bits of the halfword. EMIF_BA[1] should be connected to Memory A[0] pin.
3. Suggest to try maximum value for SETUP, STROBE, and HOLD fields in CE2FFG register first, make sure your setup work.
4.Most likely, the problem is caused by the timing. Any special requirements for setup, strobe, and hold for the EMIF device? Can you lower the EMIF clock to 16MHz too?
5.You are right, to write data to EMIF async memory correctly, the memory has to be configured as device type or strongly-ordered type using MPU
6)
I also have to add following lines of code Possibly Halcogen Bugs that toggles the EMIF data lines and EMIF address lines.
systemREG1->GPREG1 |= 0x80000000;
dmmREG->PC1 = 1 /* DATA[0] */ /*!!! should be 1 << 2 !!!*/
| (1 << 1) /* DATA[1] */ /*!!! should be 1 << 3 !!!*/
| (1 << 2) /* DATA[2] */ /*!!! etc !!!*/
| (1 << 3) /* DATA[3] */
| (1 << 4) /* DATA[4] */
| (1 << 5) /* DATA[5] */
| (1 << 6) /* DATA[6] */
| (0 << 7) /* DATA[7] */
| (0 << 8) /* DATA[8] */
| (0 << 9) /* DATA[9] */
| (0 << 10) /* DATA[10] */
| (1 << 11) /* DATA[11] */
| (0 << 12) /* DATA[12] */
| (1 << 13) /* DATA[13] */
| (1 << 14) /* DATA[14] */
| (0 << 15) /* DATA[15] */
| (0 << 16) /* DMM SYNC */
| (1 << 17) /* DMM CLK */
| (1 << 18); /* DMM ENA */
7) EMIF at 45MHz
8) mpuInit() .
9) The EMIF clock should be < 50MHz. 90MHz is out of the valid range.
10) Also the setting " DEVICE MODE" for 0x6000_0000 memory region in MPU setting. If using NORMAL mode, there are more than 1 new pulse in one nCS cycle.
11) Can you make sure that the MPU initialization function mpuInit() is actually called from the main routine? This initialization is not done by the default start-up sequence generated by HALCoGen.
