CCS/TMS570LC4357: Low Power Mode - CLKTEST, running code in SRAM

Chris Dickerson

Part Number: TMS570LC4357

Tool/software: Code Composer Studio

QJ Wang - you mentioned that I have to set CLKTEST (see in the code below) in SRAM -- how? Where is this documented? I looked at the Technical Reference and the CLKTEST section doesn't mention it. Is this setting absolutely necessary for setting a Low Power State?

/* Setup the flash banks and pump active grace periods as 7 HCLK/16 cycles*/
 flashWREG->rsvd5 /*FPAC2*/ = 0x7;

/* Bank 7 */
flashWREG->FMAC = 0x6;
flashWREG->FBAC = 0x70F;

/* Bank 0 */
flashWREG->FMAC = 0x0;
flashWREG->FBAC = 0x70F;

/* Setup flash module to change fallback modes for banks/pump to be "sleep" */
flashWREG->FBPWRMODE /*FBFALLBACK*/ = 0x00000000U
                   | (uint32)((uint32)SYS_SLEEP << 14U) /* BANK 7 */
                   | (uint32)((uint32)SYS_SLEEP << 2U)  /* BANK 1 */
                   | (uint32)((uint32)SYS_SLEEP << 0U); /* BANK 0 */

/* Disable oscillator monitoring to prevent detection of osc fail */
systemREG1->CLKTEST = 0x30A0000; // needs to be executed from SRAM

If I comment out the line setting CLKTEST, the next line that executes -- fails as well (rtiStopCounter):

/* RTI is configured to generate compare 0 interrupt every 10 seconds using 16MHz OSCIN as source */
/* Reset and restart RTI Counter 0 */
rtiStopCounter(rtiREG1, rtiCOUNTER_BLOCK0); // CCS hangs
rtiResetCounter(rtiREG1, rtiCOUNTER_BLOCK0);

systemREG1->RCLKSRC = 0x0;

/** - Setup compare 0 value. This value is compared with selected free running counter. */
rtiREG1->CMP[0U].COMPx = 4000000U;

/** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */
rtiREG1->CMP[0U].UDCPx = 4000000U;

/** - Clear all pending interrupts */
rtiREG1->INTFLAG = 0x0007000FU;

// more code...

RTI is initialized, and the help files do not mention any other calls required to execute rtiStopCounter.

over 5 years ago

0 QJ Wang over 5 years ago

TI__Guru**** 198766 points

Hi Chris,

If the flash bump and flash banks are turned off, the code in flash is not readable. You need to copy the code to SRAM before turning off the flash bank, and execute the instruction from SRAM.

0 Chris Dickerson over 5 years ago in reply to QJ Wang

Intellectual 380 points

How do you copy code to SRAM? I couldn't find this information in the documentation.

0 QJ Wang over 5 years ago in reply to Chris Dickerson

TI__Guru**** 198766 points

You have put the flash bank to sleep mode:

/* Setup flash module to change fallback modes for banks/pump to be "sleep" */

flashWREG->FBPWRMODE /*FBFALLBACK*/ = 0x00000000U

| (uint32)((uint32)SYS_SLEEP << 14U) /* BANK 7 */

| (uint32)((uint32)SYS_SLEEP << 2U) /* BANK 1 */

| (uint32)((uint32)SYS_SLEEP << 0U); /* BANK 0 */

Any access to a flash while flash pump/bank is not active, a bus error will be triggered.

0 Chris Dickerson over 5 years ago in reply to QJ Wang

Intellectual 380 points

Are you saying that my code for banks/pumps (sleep) is incorrect? Does this have something to do with copying code to SRAM to execute it ?

0 QJ Wang over 5 years ago in reply to Chris Dickerson

TI__Guru**** 198766 points

Hello,

In your code, flashWREG->FBPWRMODE = 0x00000000 is to switch the flash banks to SLEEP mode.

When the BANKx power mode is switched to a mode other than ACTIVE mode, the L2FMC will immediately apply the new power mode to the affected bank(s). While and after the bank power is switched out of ACTIVE mode, any new command (read, write, erase, etc) for inactive bank(s) will be responded with error.

0 Chris Dickerson over 5 years ago in reply to QJ Wang

Intellectual 380 points

Ok, but how do you run code from SRAM?

0 Chester Gillon over 5 years ago in reply to Chris Dickerson

Guru 92251 points

Chris Dickerson said:
Ok, but how do you run code from SRAM?

Does Placing functions in RAM help?

That article is specific to TI compilers, not sure which compiler you are using.

0 Chris Dickerson over 5 years ago in reply to Chester Gillon

Intellectual 380 points

TI ARM C/C++ Compiler v20.2.2.LTS

TI compiler -- thanks for the link.

0 QJ Wang over 5 years ago in reply to Chris Dickerson

TI__Guru**** 198766 points

Hi Chris,

Please refer to the linker CMD file in example code of CAN bootloader:

0 Chris Dickerson over 5 years ago in reply to QJ Wang

Intellectual 380 points

So, if I want to run my code, put the Hercules to sleep and later wake it up and run my code -- should the Hercules ALWAYS run ALL CODE from SRAM?

– 4MB of Program Flash With ECC
– 512KB of RAM With ECC
– 128KB of Data Flash for Emulated EEPROM With ECC

I have concern as there isn't as much RAM as program flash.

0 QJ Wang over 5 years ago in reply to Chris Dickerson

TI__Guru**** 198766 points

About lower power mode for TMS570 devices, please refer to this thread:

0 QJ Wang over 5 years ago in reply to QJ Wang

TI__Guru**** 198766 points

Putting flash bank and flash pump to sleep mode is the first step to enable the device low power mode. The clock source and clock domain should be disabled.

Since TMS570LC43x flash doesn't have bank access grace period (BAGP), and pump access grace period (PAGP), the bank and pump enters to sleep mode immediately after configuring the power mode (FBPWRMODE, FPAC1).

My understanding is that the code used to disable clock source and clock domain should be executed from SRAM.

0 Chris Dickerson over 5 years ago in reply to QJ Wang

Intellectual 380 points

Thanks QJ, I have alot to process now, I will let you know how it turns out.

Arm-based microcontrollers

Arm-based microcontrollers forum

CCS/TMS570LC4357: Low Power Mode - CLKTEST, running code in SRAM