CCS/TMS570LC4357: SafeTI library: PBIST_L2RAM_ENABLE test fails when using example code

Hello Joy,

Is the RAM ECC detection (ECC_DETECT_EN in RAMCTL) disabled before performing SRAM PBIST? 

SL_Init_Memory() is a API of the library, but the _memInit() is the memory init code generated from HALCOGen. You can use either of them. If you use APIs of the library for other tests, it's better to use SL_Init_Memory() to keep your code consistent. 

I will do a test using the library APIs.

In the sl_init.c, in the function SL_Init_ECCTCMRAM, the ECC_DETECT_EN is not specifically disabled. Instead, for the TMS570LC43x, most of the function is disabled and it states that it is "enabled by default at reset" as shown below:

Should I manually be calling any of the BF_SET calls in the sl_init.c file?

Thank you for being willing to do a test. If you could use the recommended code example from safe TI 2.4.0 that would be most helpful. 

Where should the SL_Init_Memory occur? Does it need to be after the BPIST test? 

Hello,

The RAM memory is normally initialized at startup. After initialization, the SRAM is initialized to zeros and the ECC is initialized to the correct ECC value (0x)C) for zeros. You don't need to initialize the SRAM after PBIST test.

Before starting the PBIST test, both the instruction cache and data cache should be disabled. 

Hello QJ, 

Thank you for your response. 

We have not enabled the instruction or data cache at all, or touched any ECC registers. 

In Debug: 

When we remove the mem_init that occurs right after the L2RAM BPIST check is done, we end up stuck in "prefetchEntry" area of HL_sys_intvecs.asm. 

So, it appears it's still necessary to re-init the memory after the L2RAM check is done. Or is there something else that would cause this failure?

In Release:

Still having original issue. 
Were you able to try the example code? 

I tried in debug mode, I got ECC error (expected), but I didn't PBIST error (FSRF0, and FSRF1). 

BTW, the CPU ECC logic can not be disabled for this device. My statement in my last message is not able to block the generation of ECC error. 

Can you use the linker cmd file to generate ECC? Attached is the my example.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/312/6305.HL_5F00_sys_5F00_link.cmd

software-dl.ti.com/.../index.html

Hello QJ,

Can you please elaborate on what you mean by "not able to block the generation of ECC error"?

Is it required to use the cmd file to specify a specific area for the ECC interrupts? 

Should we instead try to manually set the RAMCTRL registers to disable some of the ECC before the test? 

What is the significance of the "0xf0400000" memory address for the ECC_VEC vector? We tried adding just the ECC_VEC section and had compiler failures (see attached below)

7065.HL_sys_link.zip

Hello,

The ECC values for all of the Flash memory space (Flash banks 0 through 6) must be programmed into the Flash before the program/data can be read. This can be easily done by generating the correct values of the ECC with Linker CMD file.

ECC error checking cannot be disabled on the R5F CPU. L2RAMW wrapper has also a built-in SECDED component. Disabling ECC on the L2RAMW module will disable ECC error checking only for the ECC functions that the L2RAM handles (sub 64-bit Write Operations). All other ECC handling is done by the R5F CPU. So disabling the ECC detection on L2RAMW doesn't block the ECC checking on CPU side.

Hello QJ, 

We were able to get the L2RAM test to run; however, not when the ROM test is also enabled.

Do you have all the tests enabled when you are trying to run through the PBIST testing?

Are you using the same example code I'm using? 

Hello,

March13 is the most recommended algorithm for RAM self-test, but triple_read_slow/fast_read is used for PBIST ROM self-test.

They should not be grouped together for PBIST test.

Hello QJ

Can you explain further what you mean by "grouped together"? Can they not be run sequentially? As shown in the TI provided example?

We tried removing any optimizations for the HalCoGen created HL_startup file (previously level 2 optimizations), and that appeared to allow both tests to pass. 

Are there restrictions on using optimizations with the SafeTI or HalCoGen generated code?