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Tool/software: Code Composer Studio
I have all other SafeTI functions and checks working correctly from the Diagnostic Library, but whenever I define PBIST_L2RAM_ENABLE = 1, I get hung in self test. Setting it to a zero passes all other tests and brings me correctly into main.
I have tried with flash settings set to Auto-generate EEC and without it.
Has anyone experienced this issue or know where I might poke around to resolve it?
Mr Wang,
The PBIST_L2RAM_ENABLE comes from the sys_startup.c code from the Halcogen Safety Library example. It among others is used to define which self tests to perform at startup. Setting to 1 implements the self-test. Setting to 0 does not. When I set this to 0, I enter my main() code correctly. I isolated my issue to this by turning the self-tests on one at a time. I am just trying to determine if there is a flag or setting somewhere that may be causing my L2RAM to show this fault during self test.
Hello,
This is the PBIST API defined by the SDL:
boolean SL_SelfTest_PBIST (register SL_SelfTestType testType, register uint64 ramGroup, register uint32 algoInfo)
The PBIST controller needs to be configured separately for single-port and dual-port RAMs. The CPU RAM (L2RAM) is a single-port memory, and the March13N TwoPort Algorithm should not be used. If an algorithm is selected to run on an incompatible memory, this will result in a failure.
The contents of the L2RAM before the test will be completly lost. Your software must take care of data backup if required. Typically the PBIST tests are carried out at the beginning.
I checked the example code of SDL2.4.0, I don't see any PBIST test in HL_sys_startup.c, and don't find PBIST_L2RAM_ENABLE.
Can you post your startup.c?
Below is the code for my sys_startup. This is taken from the Halcogen safety example instructions. It appears the 1 port algorithm is used. I appreciate your help.
/*
* Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "HL_sys_common.h"
#include "HL_system.h"
#include "HL_sys_vim.h"
#include "HL_sys_core.h"
#include "HL_esm.h"
#include "HL_sys_mpu.h"
/* USER CODE BEGIN (1) */
#include "sl_api.h"
#include "sl_types.h"
#include "HL_errata.h"
#include "HL_reg_dma.h"
#include "HL_reg_can.h"
#include "HL_reg_het.h"
#include "HL_reg_htu.h"
#include "HL_reg_mibspi.h"
#include "HL_reg_adc.h"
#include "HL_reg_efc.h"
#include "HL_reg_stc.h"
#include "HL_reg_pbist.h"
#include "HL_sys_core.h"
/* USER CODE END */
/* USER CODE BEGIN (2) */
extern uint32 ulHighHandlerLoadStart;
extern uint32 ulHighHandlerLoadEnd;
extern uint32 ulHighHandlerSize;
extern uint32 ulHighHandlerStartAddr;
extern uint32 ulHighHandlerEndAddr;
void esmCallBackFunction (uint32 grp_channel, uint32 param1, uint32 param2, uint32 param3);
/* USER CODE END */
/* External Functions */
/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */
extern void __TI_auto_init(void);
/*SAFETYMCUSW 354 S MR:1.4 <APPROVED> " Startup code(main should bedeclared by the user)" */
extern void main(void);
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
/*SAFETYMCUSW 354 S MR:1.4 <APPROVED> " Startup code(Extern declaration present in the library)" */
extern void exit(void);
extern void muxInit(void);
/* USER CODE BEGIN (3) */
#define STC_ENABLE 1
#define PBIST_ROM_ENABLE 1
#define PBIST_L2RAM_ENABLE 0
#define PBIST_PERIPHRAM_ENABLE 1
#define PBIST_VIM_ENABLE 1
#define L2RAMECCCHECK_ENABLE 1
#define FLASHECCCHECK_ENABLE 1
#define PERIPHRAMECCCHECK_ENABLE 1
#define EFUSETEST_ENABLE 1
#define CCMR5TEST_ENABLE 1
/* USER CODE END */
/* Startup Routine */
void _c_int00(void);
/* USER CODE BEGIN (4) */
/* USER CODE END */
#pragma CODE_STATE(_c_int00, 32)
#pragma INTERRUPT(_c_int00, RESET)
#pragma WEAK(_c_int00)
void _c_int00(void)
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
switch(getResetSource())
{
case POWERON_RESET:
case DEBUG_RESET:
case EXT_RESET:
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* Initialize L2RAM to avoid ECC errors right after power on */
_memInit_();
/* USER CODE BEGIN (7) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* USER CODE BEGIN (8) */
/* USER CODE END */
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* USER CODE BEGIN (9) */
/* USER CODE END */
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (10) */
//test if startup code executes
/* USER CODE END */
/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case. */
if ((esmREG->SR1[2]) != 0U)
{
esmGroup3Notification(esmREG,esmREG->SR1[2]);
}
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
/* USER CODE BEGIN (11) */
SL_ESM_Init(&esmCallBackFunction);
_enable_interrupt_();
#if (PBIST_ROM_ENABLE == 1) || (PBIST_L2RAM_ENABLE == 1) || (PBIST_PERIPHRAM_ENABLE == 1)
/* Workaround for the Errata PBIST#4 */
errata_PBIST_4();
#endif
#if PBIST_ROM_ENABLE == 1
{
boolean retVal;
/* Start PBIST on STC and PBIST ROM */
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
PBIST_RAMGROUP_01_PBIST_ROM |
PBIST_RAMGROUP_02_STC1_1_ROM_R5 |
PBIST_RAMGROUP_03_STC1_2_ROM_R5 |
PBIST_RAMGROUP_04_STC2_ROM_NHET,
PBISTALGO_TRIPLE_READ_FAST_READ |
PBISTALGO_TRIPLE_READ_SLOW_READ);
if(retVal == false){while(1);}
}
#endif
#if EFUSETEST_ENABLE == 1
{
boolean retVal;
SL_EFuse_Config config;
uint32 efcStatus;
config.numPatterns = 600u;
config.seedSignature = 0x5362F97Fu;
config.failInfo.stResult= ST_FAIL;
config.failInfo.failInfo= EFUSE_ERROR_NONE;
efcStatus = efcREG->ERR_STAT;
if(efcStatus == 0x0U)
{
/* Run Stuck At Zero Test (param2=TRUE - Wait for complete) */
retVal = SL_SelfTest_EFuse(EFUSE_SELF_TEST_STUCK_AT_ZERO, TRUE, &config);
if(retVal == false){while(1);}
if(config.failInfo.stResult == ST_PASS)
{
/* Run efuse self test (param2=TRUE - Wait for complete) */
retVal = SL_SelfTest_EFuse(EFUSE_SELF_TEST_ECC, TRUE, &config);
if(retVal == false){while(1);}
if(config.failInfo.stResult != ST_PASS)
{
/* Selftest failed - Class 2 error */
while(1);
}
}
else
{
/* Stuck At Zero test failed - Class 2 error */
while(1);
}
}
else
{
if (efcStatus == 0x15U)
{
/* Run efuse self test (param2=TRUE - Wait for complete) */
retVal = SL_SelfTest_EFuse(EFUSE_SELF_TEST_ECC, TRUE, &config);
if(retVal == false){while(1);}
if(config.failInfo.stResult != ST_PASS)
{
/* Selftest failed - Class 2 error */
while(1);
}
else
{
/* Selftest passed - Class 3 error */
while(1);
}
}
else
{
/* Class 2 error */
while(1);
}
}
}
#endif
#if PBIST_ROM_ENABLE == 1
{
SL_PBIST_FailInfo pbistStatus;
/* Wait for PBIST on ROM to complete */
while(SL_SelfTest_Status_PBIST(&pbistStatus) == FALSE);
SL_SelfTest_PBIST_StopExec();
if(pbistStatus.stResult != ST_PASS)
{
/* PBIST fail */
while(1);
}
/* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
vimREG->INTREQ2 = 0x00200000;
}
#endif
#if PBIST_L2RAM_ENABLE == 1
{
/* Run PBIST on L2RAM */
SL_SelfTest_PBIST( PBIST_EXECUTE,
PBIST_RAMGROUP_29_L2RAMW |
PBIST_RAMGROUP_30_L2RAMW,
PBISTALGO_MARCH13N_1PORT);
while((systemREG1->MSTCGSTAT & 0x1u) == 0x0u);
if ((pbistREG->FSRF0 == 0u) && (pbistREG->FSRF1 == 0u))
{
/* PBIST pass */
}
else
{
/* PBIST fail */
while(1);
}
SL_SelfTest_PBIST_StopExec();
_memInit_();
/* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
vimREG->INTREQ2 = 0x00200000;
}
#endif
#if PBIST_PERIPHRAM_ENABLE == 1
{
boolean retVal;
/* Run PBIST on dual port memories (except VIM) */
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
PBIST_RAMGROUP_05_AWM1 |
PBIST_RAMGROUP_06_DCAN1 |
PBIST_RAMGROUP_07_DCAN2 |
PBIST_RAMGROUP_08_DMA |
PBIST_RAMGROUP_09_HTU1 |
PBIST_RAMGROUP_10_MIBSPI1 |
PBIST_RAMGROUP_11_MIBSPI2 |
PBIST_RAMGROUP_12_MIBSPI3 |
PBIST_RAMGROUP_13_NHET1 |
PBIST_RAMGROUP_16_RTP |
PBIST_RAMGROUP_18_AWM2 |
PBIST_RAMGROUP_19_DCAN3 |
PBIST_RAMGROUP_20_DCAN4 |
PBIST_RAMGROUP_21_HTU2 |
PBIST_RAMGROUP_22_MIBSPI4 |
PBIST_RAMGROUP_23_MIBSPI5 |
PBIST_RAMGROUP_24_NHET2 |
//PBIST_RAMGROUP_25_FTU | /* Enable only in TMS device */
//PBIST_RAMGROUP_26_FRAY_INBUF_OUTBUF | /* Enable only in TMS device */
PBIST_RAMGROUP_27_CPGMAC_STATE_RXADDR |
PBIST_RAMGROUP_28_CPGMAC_STAT_FIFO,
PBISTALGO_MARCH13N_2PORT);
if(retVal == false){while(1);}
}
#endif
#if L2RAMECCCHECK_ENABLE == 1
{
boolean retVal;
SL_SelfTest_Result result;
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &result);
if(retVal == false){while(1);}
if(result != ST_PASS)
{
/* Test fail */
while(1);
}
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &result);
if(retVal == false){while(1);}
if(result != ST_PASS)
{
/* Test fail */
while(1);
}
}
#endif
#if FLASHECCCHECK_ENABLE == 1
{
boolean retVal;
SL_SelfTest_Result result;
/* Flash test needs to be run from a RAM location. Copy flash test to RAM */
uint32 i;
uint32 size=(uint32)&ulHighHandlerSize;
for(i=0;i<size;i++)
{
((char *)&ulHighHandlerStartAddr)[i] =((char *)&ulHighHandlerLoadStart)[i];
}
retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_1BIT, TRUE, &result);
if(retVal == false){while(1);}
if(result != ST_PASS)
{
/* Test fail */
while(1);
}
retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, TRUE, &result);
if(retVal == false){while(1);}
if(result != ST_PASS)
{
/* Test fail */
while(1);
}
}
#endif
#if PBIST_PERIPHRAM_ENABLE == 1
{
SL_PBIST_FailInfo pbistStatus;
while(SL_SelfTest_Status_PBIST(&pbistStatus) == FALSE);
SL_SelfTest_PBIST_StopExec();
if(pbistStatus.stResult != ST_PASS)
{
/* PBIST fail */
while(1);
}
/* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
vimREG->INTREQ2 = 0x00200000;
/* Memory Init for MIBSPI */
mibspiREG1->GCR0 = 0x1U;
mibspiREG2->GCR0 = 0x1U;
mibspiREG3->GCR0 = 0x1U;
mibspiREG4->GCR0 = 0x1U;
mibspiREG5->GCR0 = 0x1U;
while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
mibspiREG1->MIBSPIE = 1;
mibspiREG1->PAR_ECC_CTRL = (mibspiREG1->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;
while ((mibspiREG2->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
mibspiREG2->MIBSPIE = 1;
mibspiREG2->PAR_ECC_CTRL = (mibspiREG2->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;
while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
mibspiREG3->MIBSPIE = 1;
mibspiREG3->PAR_ECC_CTRL = (mibspiREG3->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;
while ((mibspiREG4->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
mibspiREG4->MIBSPIE = 1;
mibspiREG4->PAR_ECC_CTRL = (mibspiREG4->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;
while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
mibspiREG5->MIBSPIE = 1;
mibspiREG5->PAR_ECC_CTRL = (mibspiREG5->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;
/* Enable ECC for other RAMs */
dmaREG->DMAPCR = 0xA;
hetREG1->PCR = 0xA;
htuREG1->PCR = 0xA;
hetREG2->PCR = 0xA;
htuREG2->PCR = 0xA;
canREG1->CTL = (canREG1->CTL & 0xFFFFC3FF) | (0xA << 10);
canREG2->CTL = (canREG2->CTL & 0xFFFFC3FF) | (0xA << 10);
canREG3->CTL = (canREG3->CTL & 0xFFFFC3FF) | (0xA << 10);
canREG4->CTL = (canREG4->CTL & 0xFFFFC3FF) | (0xA << 10);
/* Initialize CAN module before using it */
canREG1->CTL &= ~(uint32)(0x00000041U);
canREG2->CTL &= ~(uint32)(0x00000041U);
canREG3->CTL &= ~(uint32)(0x00000041U);
canREG4->CTL &= ~(uint32)(0x00000041U);
adcREG1->PARCR = 0xA;
adcREG2->PARCR = 0xA;
/* Memory Init for all RAMs (except VIM) with correct ECC */
SL_Init_Memory( RAMTYPE_DMA_RAM |
RAMTYPE_NHET1 |
RAMTYPE_HET_TU1 |
RAMTYPE_NHET2 |
RAMTYPE_HET_TU2 |
RAMTYPE_DCAN1_RAM |
RAMTYPE_DCAN2_RAM |
RAMTYPE_DCAN3_RAM |
RAMTYPE_DCAN4_RAM |
RAMTYPE_MIBSPI1_RAM |
RAMTYPE_MIBSPI2_RAM |
RAMTYPE_MIBSPI3_RAM |
RAMTYPE_MIBSPI4_RAM |
RAMTYPE_MIBSPI5_RAM |
RAMTYPE_MIBADC1_RAM |
RAMTYPE_MIBADC2_RAM );
}
#endif
#if PERIPHRAMECCCHECK_ENABLE == 1
{
if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN1) == false)
{
while(1);
}
if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_2BIT, SL_DCAN1) == false)
{
while(1);
}
if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN2) == false)
{
while(1);
}
if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_2BIT, SL_DCAN2) == false)
{
while(1);
}
if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN3) == false)
{
while(1);
}
if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_2BIT, SL_DCAN3) == false)
{
while(1);
}
if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN4) == false)
{
while(1);
}
if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_2BIT, SL_DCAN4) == false)
{
while(1);
}
if(SL_SelfTest_DMA(DMA_ECC_TEST_MODE_1BIT) == false)
{
while(1);
}
if(SL_SelfTest_DMA(DMA_ECC_TEST_MODE_2BIT) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI1) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI1) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI2) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI2) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI3) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI3) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI4) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI4) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI5) == false)
{
while(1);
}
if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI5) == false)
{
while(1);
}
}
#endif
#if CCMR5TEST_ENABLE == 1
{
boolean retVal;
SL_CCMR5F_FailInfo failInfo;
retVal = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_SELF_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_SELF_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_PDCOMP_SELF_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_PDCOMP_SELF_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_PDCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_PDCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_INMCOMP_SELF_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_INMCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
retVal = SL_SelfTest_CCMR5F(CCMR5F_INMCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
if(retVal == false){while(1);}
if(failInfo.stResult != ST_PASS)
{
while(1);
}
}
#endif
#if PBIST_VIM_ENABLE == 1
{
boolean retVal;
SL_PBIST_FailInfo pbistStatus;
/* Start PBIST on STC and PBIST ROM */
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
PBIST_RAMGROUP_01_PBIST_ROM |
PBIST_RAMGROUP_02_STC1_1_ROM_R5 |
PBIST_RAMGROUP_03_STC1_2_ROM_R5 |
PBIST_RAMGROUP_04_STC2_ROM_NHET,
PBISTALGO_TRIPLE_READ_FAST_READ |
PBISTALGO_TRIPLE_READ_SLOW_READ);
if(retVal == false){while(1);}
/* Wait for PBIST on ROM to complete */
while(SL_SelfTest_Status_PBIST(&pbistStatus) == FALSE);
SL_SelfTest_PBIST_StopExec();
if(pbistStatus.stResult != ST_PASS)
{
/* PBIST fail */
while(1);
}
/* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
vimREG->INTREQ2 = 0x00200000;
}
#endif
/* USER CODE END */
/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();
/* Initialize VIM table */
vimInit();
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* Configure system response to error conditions signaled to the ESM group1 */
/* This function can be configured from the ESM tab of HALCoGen */
esmInit();
/* USER CODE BEGIN (13) */
#if STC_ENABLE == 1
{
SL_STC_Config stcSelfTestConfig;
stcSelfTestConfig.stcClockDiv = 2; /* STC Clock divider = 1 */
stcSelfTestConfig.intervalCount = 1; /* One interval only */
stcSelfTestConfig.restartInterval0 = TRUE; /* Start from interval 0 */
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; /* Timeout counter*/
SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
while(1); /* STC failed to start */
}
#endif
/* USER CODE END */
break;
case OSC_FAILURE_RESET:
/* USER CODE BEGIN (14) */
/* USER CODE END */
break;
case WATCHDOG_RESET:
/* USER CODE BEGIN (15) */
/* USER CODE END */
break;
case CPU0_RESET:
// case CPU1_RESET:
/* USER CODE BEGIN (16) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* USER CODE BEGIN (18) */
/* USER CODE END */
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (19) */
#if STC_ENABLE == 1
if ((stcREG1->STCSCSCR & 0xFU) == 0xAU)
{
/* check if the self-test fail bit is set */
if ((stcREG1->STCGSTAT & 0x3U) != 0x3U)
{
/* STC self-check has failed */
while(1);
}
/* STC self-check has passed */
else
{
/* clear self-check mode */
stcREG1->STCSCSCR = 0x05U;
/* clear STC global status flags */
stcREG1->STCGSTAT = 0x3U;
/* clear ESM group1 channel 27 status flag */
esmREG->SR1[0U] = 0x08000000U;
{
SL_STC_Config stcSelfTestConfig;
stcSelfTestConfig.stcClockDiv = 0; /* STC Clock divider = 1 */
stcSelfTestConfig.intervalCount = 1; /* One interval only */
stcSelfTestConfig.restartInterval0 = TRUE; /* Start from interval 0 */
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; /* Timeout counter*/
SL_SelfTest_STC(STC1_RUN, TRUE, &stcSelfTestConfig);
while(1); /* STC failed to start */
}
}
}
/* CPU reset caused by CPU self-test completion */
else if ((stcREG1->STCGSTAT & 0x1U) == 0x1U)
{
/* Self-Test Fail flag is set */
if ((stcREG1->STCGSTAT & 0x2U) == 0x2U)
{
/* Call CPU self-test failure handler */
while(1);
}
/* CPU self-test completed successfully */
else
{
/* clear STC global status flag */
stcREG1->STCGSTAT = 0x1U;
/* Continue start-up sequence after CPU STC completed */
}
}
/* CPU reset caused by software writing to CPU RESET bit */
else
{
/* Add custom routine here to handle the case where software causes CPU reset */
}
#endif
/* USER CODE END */
break;
case SW_RESET:
/* USER CODE BEGIN (20) */
/* USER CODE END */
break;
default:
/* USER CODE BEGIN (21) */
/* USER CODE END */
break;
}
/* USER CODE BEGIN (22) */
/* USER CODE END */
_mpuInit_();
/* USER CODE BEGIN (23) */
/* USER CODE END */
/* initialize global variable and constructors */
__TI_auto_init();
_cacheEnable_();
/* USER CODE BEGIN (24) */
/* USER CODE END */
/* USER CODE BEGIN (25) */
/* USER CODE END */
/* USER CODE BEGIN (26) */
/* USER CODE END */
/* call the application */
/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
main();
/* USER CODE BEGIN (27) */
/* USER CODE END */
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
exit();
}
/* USER CODE BEGIN (28) */
/* USER CODE END */
/* USER CODE BEGIN (29) */
void esmCallBackFunction (uint32 grp_channel, uint32 param1, uint32 param2, uint32 param3)
{
}
/* USER CODE END */
Got it, thanks. This is the HALCoGen example: safetyLib.c. I will do a test.
Hello,
Do you know where the code hung? Is it hung in SL_SelfTest_PBIST(..) or hung at while(1) loop ?
#if PBIST_L2RAM_ENABLE == 1
{
/* Run PBIST on L2RAM */
SL_SelfTest_PBIST( PBIST_EXECUTE,
PBIST_RAMGROUP_29_L2RAMW |
PBIST_RAMGROUP_30_L2RAMW,
PBISTALGO_MARCH13N_1PORT);
while((systemREG1->MSTCGSTAT & 0x1u) == 0x0u);
if ((pbistREG->FSRF0 == 0u) && (pbistREG->FSRF1 == 0u))
{
/* PBIST pass */
}
else
{
/* PBIST fail */
while(1);
}
SL_SelfTest_PBIST_StopExec();
_memInit_();
/* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
vimREG->INTREQ2 = 0x00200000;
}
#endif