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TMS570LC4357: PBIST L2RAM Test (sourced from SafeTI LIbrary) always fails

Robert Barton1
Prodigy 40 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

The TMS570LC4357 PBIST L2RAM Test (sourced from SafeTI LIbrary) always fails.  Exact same question as found in previous TI questions posted below:

e2e.ti.com/.../ccs-tms570lc4357-safeti-library-pbist_l2ram_enable-test-fails-when-using-example-code

or

https://e2e.ti.com/support/microcontrollers/hercules/f/hercules-safety-microcontrollers-forum/857006/ccs-tms570lc4357-tms570lc4357-pbist-on-l2ram-failing

Asking again because no answer/solution was actually ever provided to the previous questions.  Why does the TI provided code within the SafeTI library PBIST L2RAM test always fail the test and hang up the software in a while loop due to the L2RAM error? Is there something actually wrong with the TMS570LC4357 RAM? Is there some code/assembly that can be placed directly prior to the L2RAM test execution to shutdown cache so that the test can pass? I am looking for a specific solution and not some general statement about selecting the wrong algorithm causing a test failure.  Does TI stand by TMS570LC4357 part and the SafeTI library code?

  • 0
    TI__Mastermind 49120 points

    Do you see the self-test fail even when you disable all compiler optimizations? The self-test routines use several "dummy reads" which are necessary for the correct operation of the self-test routines.

  • 0
    Prodigy 40 points

    Yes the self-test fails even when diabling all compiler optimizations.

  • 0 in reply to Robert Barton1
    TI__Mastermind 49120 points

    The demo example does not include an example of running PBIST on the L2 RAM. There is a comment though for running PBIST on cached memories.

    Can you try executing PBIST on L2 RAM before enabling the cache or even before configuring the MPU? These steps are done as part of the suggested start-up routine in the example demo application.

  • 0 in reply to Sunil Oak
    Prodigy 40 points

    I attempted several different iterations(moving the test prior to enabling cache and eliminating some MPU configuration commands), with no improvement in the result.  Was not able to completely eliminate some of the MPU configuration routines or PBIST would not even run.

  • 0 in reply to Robert Barton1
    TI__Mastermind 49120 points

    I am attaching a CCS project that runs PBIST on the L2 RAM. Hope this helps.

    LC4357_PBIST.zip

  • 0 in reply to Sunil Oak
    Prodigy 40 points

    This PBIST L2 RAM test successfully passes, but the application is not able to run after the PBIST L2 RAM test is enable. 

    After the PBIST L2 RAM test completes, the main() application starts initializing additional interfaces and then gets stuck in the HL_sys_intvecs.asm, interrupt vectors, b _dabort section which in turn calls the dabort.asm _dabort section, which then calls the ramErrorFound and then goes back to interrupt vectors section in a tight loop so that nothing else runs.

    Not sure how to prevent the RAM error condition that only occurs after the PBIST L2 RAM test is enabled?

  • 0 in reply to Robert Barton1
    TI__Mastermind 49120 points

    The issue could be with the PBIST engine not "releasing" the L2 RAM so that other bus masters can access it. The pbistStop() function generated by HCG is missing a reset for the PBIST controller. The function below is the updated pbistStop(). Please update the routine generated by HALCoGen to match the following.

    void pbistStop(void)
    {
    /* USER CODE BEGIN (20) */
        pbistREG->PACT = 0x0U;
        systemREG1->MSTGCR &= 0xFFFFFFF0U;
        systemREG1->MSTGCR |= 0xAU;
        systemREG1->MSTGCR &= 0xFFFFFFF0U;
        systemREG1->MSTGCR |= 0x5U;
    /* USER CODE END */
    }