MSP430F1101A: 3 wire SPI (CS, SCK, MOSI/MISO)

I haven't seen any examples, and I haven't tried it myself. I only know about it from reading data sheets. The notion would be:

1) Set the MOSI GPIO as an input (PxDIR). 

2) Just before you send a byte where the master owns the bus, set the PxSEL bit for the MOSI pin to let the USCI control it. When the byte is sent (UCBUSY=0 or RXIFG=1), clear the PxSEL bit for MOSI.

3) You can probably leave the MISO pin connected to the USCI all the time, since it's an input.

Managing (2) would be done referring to the (slave) data sheet waveforms. 

It seems probable that there will be brief moments of bus contention at the switch-over times; just try to keep them short. I've seen current-limiting resistors used (MOSI) to reduce their significance.

Let us know how it turns out.