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Original question:

MSP430F2122: PWM Output on P2.3 & P2.4 Setup for Inverse Operation

MSP430F2122: PWM Output on P2.3 & P2.4 in sync with P3.7 &P3.6

Joshua Lind
Prodigy 40 points
Part Number: MSP430F2122


I'm attempting to make the output on P3.7 and P3.6 be in sync with P2.4 & P2.3 but maintain a 50% or near 50% duty cycle. I'm struggling a little to set this up. Any pointers or suggestions are welcomed. 

  • 0
    Guru 100785 points

    What do you have so far?

    Also, you should probably say exactly what "sync" means. To some people it means "common timebase" and to others "common frequency".

    It is possible to get two timers to run on the same timebase, but it's tricky (you need to count CPU clocks), and you don't want to do it often.

    TA1.0 (P3.6) is pretty much limited to OUTMOD=4, which gives you 50% duty but at half the frequency.

  • 0 in reply to Bruce McKenney
    Prodigy 40 points

    It appears setting up the second timer and matching the frequency may work fine. However, I've noticed when I attempt to stop the PWM by setting the duty to 0, or stopping the timer TA1CTL = TASSEL_2 + MC_0;  I sometimes get left with the PWM pin in a high state. I know this is a little off topic What is the best way to stop the PWM and ensure the pin is left low?

  • 0 in reply to Joshua Lind
    Guru 100785 points

    Stopping the timer (as you have seen) freezes it, rather than resetting it.

    To stop (low) the PWM RIght Now, Try something like:

    > TA1CCTL1 = (0*OUT)|OUTMOD_0;   // Stop the PWM (low)

    You can even let the timer continue running, though you'll want to be conscious of the effect when you set OUTMOD>0 in mid-cycle later.

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