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MSP430FR2433: Pending IFGs

Part Number: MSP430FR2433

Can more than one flag simultaneously appear to be set in the P1IFG register? In other words, can flags for channels 1, 2, 3, and 4 be set while channels 0, 5, 6, and 7 appear to be cleared?

  • The IFG being set is the first step in the process of triggering an interrupt. The second being the mask of the IE register.

  • Yes, I know that. Perhaps my question is too vague. Yes, too vague. I'm going to rewrite it.

  • The IFG being set causes an interrupt, not the other way around. So if you have multiple port pins configured to generate interrupts and they all get triggered at the same time, all of their IFG bits will get set and then an interrupt happens.

    This isn't something I would worry about too much since in the normal course of things it wouldn't be too likely for two to be set at once. Just let the IV register sort them out and handle them one at a time.

  • Dave:

    I want to be clear about this. I'm not talking about the IVR. I'm talking about the P1IFG register. And you are saying that "if all port pins get simultaneously triggered, then all IFG bits will be simultaneously set." Is that correct?

    And there is no priority filter applied to all those P1 IFGs when they are simultaneously set in the P1IFG register. Is that correct?

    And those two behaviors apply across all MSP430s...is that correct too?

  • Since the IFG bits follow the input pins, of course they will all get set if the input conditions are satisfied.

    Since all pins on a port source a single interrupt, there is no priority. The IV register does have a priority system but that is just for figuring out which it will return next if more than one IFG is set.

  • David:

    This is one of those questions which seem to have an obvious answer. I just wanted my understanding to be accurate.

    Thank you for being patient with me.

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