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MSP430FR5969: SPi

Part Number: MSP430FR5969


    UCB0CTLW0 |= UCSWRST;

    UCB0CTLW0 |= UCSSEL_2;
    UCB0BRW = 10;
    UCB0CTLW0 |= UCSYNC;
    UCB0CTLW0 |= UCMST;


    P1SEL1 |= BIT6 + BIT7;
    P1SEL0 |= ~BIT6 + ~BIT7;
    P2SEL1 |= BIT2;
    P2SEL0 &= BIT2;
    PM5CTL0 &= LOCKLPM5;
    UCB0IFG &= ~UCTXIFG;
    UCB0CTLW0 &= ~UCSWRST;
    UCB0IE |= UCTXIE;

    P1SEL1 |= BIT6 + BIT7;

    SLAVE_CS_DIR |= SLAVE_CS_PIN;
    SLAVE_CS_OUT |= SLAVE_CS_PIN;

Hi im trying to use SPI at UCB0, (maser / 3 pin / sync) it is any mistake in this init? Im new in msp

  • >  P1SEL0 |= ~BIT6 + ~BIT7;

    This doesn't set those bits to 0. Try:

    >  P1SEL0 &= ~(BIT6 + BIT7);

    -----

    >  P2SEL0 &= BIT2;

    Similarly. Try:

    >  P2SEL0 &= ~BIT2;

    -----

    You've set (left) UCCKPH=0. This bit is defined opposite to CPHA, so if your device expects CPHA=0 (which is very common), you should

    >     UCB0CTLW0 |= UCCKPH;    // CPHA=0

    -----

    You haven't shown the rest of your program, but I notice that you're working with the TXIE/TXIFG bits. 

    1) You've cleared TXIFG, so you won't get an initial interrupt to trigger the first byte. That means you'll have to write the first byte to TXBUF without looking.

    2) Generally, with a fast SPI (BRW=10 counts I think), I suggest not using interrupts at all, since the bookkeeping and ISR overhead will use up anything you save.

  • Ok thx. i will try without interrupts, and give to know about results

  • Thx, i use your function, but not help, maybe is some other problem. Im init MAX41460 and i try port devkit producer code.

    void initMAX(){
    
        set_reg(0x0A, 0x03);
        set_reg(0x00, 0x95);
        set_reg(0x06, 0x90);
        maxSetFreq(433920000);
        set_reg(0x0A, 0x00);
    
    }
    
    
    void maxSoftReset(){
    
        set_reg(0x17, 0x01);
        __delay_cycles(100);
        set_reg(0x17, 0x00);
        __delay_cycles(1000);
    
    }
    
    void maxSetFreq(uint32_t freq){
    
        float temp_freq;
        uint32_t fin_freq;
    
    
        temp_freq = (float)freq / 1000000;
        temp_freq *= 65536.0;
        temp_freq /= 16;
        fin_freq = (uint32_t)temp_freq;
    
        uint8_t temp = fin_freq >> 16;
        set_reg(0x0B, temp);
        temp = fin_freq >> 8;
        set_reg(0x0c, temp);
        temp = fin_freq;
        set_reg(0x0d, temp);
    
    }
    void set_reg(uint8_t reg, uint8_t value)
    {
        SLAVE_CS_OUT &= ~(SLAVE_CS_PIN);
        reg &= 0x7e;
        spix(reg);        // Register to set
        spix(value);      // Value to set it to
        SLAVE_CS_OUT |= (SLAVE_CS_PIN);
        return;
    }


    Producer code, ctx is spi handle
    void ismtx_soft_reset ( ismtx_t *ctx )
    {
        ismtx_generic_write( ctx, ISMTX_REG_CFG8, 0x01 );
        Delay_100ms(  );
        ismtx_generic_write( ctx, ISMTX_REG_CFG8, 0x00 );
        Delay_1sec(  );
    }
    
    err_t ismtx_default_cfg ( ismtx_t *ctx )
    {
        ismtx_generic_write( ctx, ISMTX_REG_CFG6, 0x03 );
        if ( ISM_TX_MODULATION_FSK == ctx->modulation )
        {
            ismtx_generic_write( ctx, ISMTX_REG_CFG1, 0x95 );
            ismtx_generic_write( ctx, ISMTX_REG_PA1, 0x90 );
            ismtx_set_frequency( ctx, 433920000 );
            ismtx_set_cfg( ctx, ISMTX_CFG_FSK_SHAPE, ISMTX_FSK_SHAPE_ENABLED );
            ismtx_adjust_frequency_deviation( ctx, 40000 );
        }   
        else if ( ISM_TX_MODULATION_ASK == ctx->modulation )
        {
            ismtx_generic_write( ctx, ISMTX_REG_CFG1, 0x90 );
            ismtx_generic_write( ctx, ISMTX_REG_PA1, 0x87 );
            ismtx_set_frequency( ctx, 433920000 );
        }
        else
        {
            return ISMTX_ERROR;
        }
        
        ismtx_generic_write( ctx, ISMTX_REG_CFG6, 0x00 );
        
        return ISMTX_OK;
    }
    
    err_t ismtx_set_frequency ( ismtx_t *ctx, uint32_t freq )
    {
        float temp_freq;
        uint32_t fin_freq;
    
        if ( ( freq > MAX_FREQ ) || ( freq < MIN_FREQ ) )
        {
            return ISMTX_PARAMETER_ERROR;
        }
    
        temp_freq = ( float )freq / MEGA;
        temp_freq *= CONST_MOD_FREQ;
        temp_freq /= CRYSTAL_FREQ;
        fin_freq = ( uint32_t )temp_freq;
    
        ismtx_generic_write( ctx, ISMTX_REG_PLL3, ( fin_freq >> 16 ) );
        ismtx_generic_write( ctx, ISMTX_REG_PLL4, ( fin_freq >> 8 ) );
        ismtx_generic_write( ctx, ISMTX_REG_PLL5, fin_freq );
    
        return ISMTX_OK;
    }
    err_t ismtx_generic_write ( ismtx_t *ctx, uint8_t reg, uint8_t data_in )
    {
        uint8_t tx_buf[ 257 ];
        uint8_t cnt;
    
        tx_buf[ 0 ] = reg & 0x7F;
        tx_buf[ 1 ] = data_in;
    
        spi_master_select_device( ctx->chip_select );
        err_t error_flag = spi_master_write( &ctx->spi, tx_buf, 2 );
        spi_master_deselect_device( ctx->chip_select );
    
        return error_flag;
    }

  • What does your code do? How do you tell that it isn't working?

    Are you using spix() to implement spi_master_write(), or is your first code mixed in with the second? 

    [Edit: Did you set UCCKPH=1? MAX41460 data sheet Fig 3 says you need that.]

  • spix is used for set_reg, and for raw data sending, just check spi pins at osciloskop, looks ok.
    Eval kit with MAX41460 have data led so i think it should show anything.



  • You might try reading back the registers you set. I think you'll have to set CFG6:FOURWIRE=1 to get SDO to work.

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