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MSP430F5438A: Multi-master issue

Madhav Malaviya
Prodigy 130 points

Part Number: MSP430F5438A
Other Parts Discussed in Thread: UCD90120A,

Hi,

I am using one of the I2C from MSP430F5438A  and on the same I2C line power sequencers (UCD90120A) are connected which are programmed through USB adapter using Fusion power designer tool.

We are using one external header to program power sequencers from fusion power designer tool separately.

And both MSP430F5438A and external header are connected to one switch which is used to decide whether to access I2C from MSP430F5438A or from External header to program UCDs.

We are controlling switch via one gpio from Msp430F5438A. 

if that GPIO = 1 then msp430f5438a can access I2C line (external header can't) if same GPIO = 0 then the external header can access I2C (MSP430F5438A can't) to program UCD90120A via USB adapter 

So as of now value of GPIO is deciding whether to access I2C from MSP430F5438A or from USB adapter through Fusion design tool. 

So my question is, Is it possible to implement multi-master mechanism from MSP430F5438A ??

  • 0
    Guru 26095 points

    I2C is inherently multi-master. Each transaction begins with the master arbitrating for access to the bus before issuing a start condition.

  • 0
    TI__Mastermind 27190 points

    David is correct, I2C in its concept can have multiple controllers and multiple targets on one I2C bus.  

  • 0 in reply to Luke Ledbetter
    Prodigy 130 points

    Hi David and Luke,

    Thanks for your reply.

    To implement multi-master on I2C line both master(MSP430F5438A and USB adapter in my case) should active at same time. But here It will not happen

    because I am using GPIO already to decide which master will access I2C line. So at a time only one master can access I2C line.

    So is my understanding correct that If I use GPIO to select master access then I can not implement multi-master in my case?

    or If I wanted to implement multi-master then do I have to change hardware? 

  • 0 in reply to Madhav Malaviya
    Guru 102665 points

    If you have only one master (at a time) on the bus, it seems that multi-master is not relevant. Or did I misunderstand your question?

    I am curious how this GPIO works -- what do the USCI pins see when it is asserted? Does it look like a vallid I2C open-drain-with-pullups bus? 

  • 0 in reply to Bruce McKenney
    Prodigy 130 points

    Hi Bruce

    Right now we are one GPIO which is configured as a output. we are controlling this GPIO by giving 1 and 0

    if GPIO = 1, MSP will act as a master

    if GPIO = 0, USB adapter will act as a master.

    So as of now value of GPIO will will decide  which master will access the I2C line.

    So yes at a time we are accessing only one master.

  • 0 in reply to Madhav Malaviya
    Guru 102665 points

    Then I'm not sure I understand the question. Do you want to get rid of the GPIO interlock?

    According to the User Guide (SLAU208Q) the USCI is capable of operating multi-master when UCMM=1. The procedures are slightly different -- you should set UCMST=1 for each transaction, and be prepared for a UCALIFG [Ref (e.g.) User Guide Fig 38-12, the box down at the bottom.]. [Disclaimer: I haven't used a multi-master bus on an MSP430, though I am familiar with the mechanism.]

  • 0 in reply to Bruce McKenney
    Prodigy 130 points

    Hi Bruce

    I do not wanted to change the GPIO configuration.

    Here in my application only one master can access I2C at a time. So we can not use multi-master, Is it right?

    For multi-master both master should be active on the bus at same time, Is it correct?

  • +1 in reply to Madhav Malaviya
    Guru 102665 points

    No. Multi-master ("Arbitration") is a mechanism for preventing two masters from starting transactions at the same time. By monitoring the bus, one of them can determine that it is not actually the master, and it halts its transaction. The mechanism goes a little further, and allows the "losing" master to be addressed as a slave (so you could in theory have a bus with only the two masters).

    If the two masters never try to "talk" at the same time (or there is actually only one master) these collisions don't occur, and activity looks like that on an ordinary I2C bus. I'm not quite sure why the USCI makes this feature optional (UCMM bit).

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