MSP430FR5994: Timer_B0 and eUSCI_B interrupt priority problem

The first place I would look is the I2C code, but I don't see any here. I would be looking for

1) spin-loops (or equivalent) which keep execution in the ISR for a long time. 

2) An LPM wakeup sequence which accidentally disables interrupts (GIE) in main e.g. "__bic_SR_register_on_exit(LPM0_bits | GIE)". [Small but significant typo.]

Unsolicited: "seconds" should be declared "volatile".

Hey Bruce,

Thanks for the reply.Could you please let me know how i can tackle this spinloop problem and LPM disable GIE issue and here is i2c code

#include <msp430.h> 
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>

//******************************************************************************
// Pin Config ******************************************************************
//******************************************************************************

#define LED_OUT     P1OUT
#define LED_DIR     P1DIR
#define LED0_PIN    BIT0
#define LED1_PIN    BIT1

//******************************************************************************
// Example Commands ************************************************************
//******************************************************************************

#define SLAVE_ADDR  0x53

/* CMD_TYPE_X_SLAVE are example commands the master sends to the slave.
 * The slave will send example SlaveTypeX buffers in response.
 *
 * CMD_TYPE_X_MASTER are example commands the master sends to the slave.
 * The slave will initialize itself to receive MasterTypeX example buffers.
 * */

#define CMD_TYPE_0_SLAVE      0x00
#define CMD_TYPE_1_SLAVE      1
#define CMD_TYPE_2_SLAVE      2

#define Power_CTL             0x2D
#define Data_Rate             0x2C
#define Data_Format           0x31

#define X0_Reg                0x32
#define X1_Reg                0x33
#define Y0_Reg                0x34
#define Y1_Reg                0x35
#define Z0_Reg                0x36
#define Z1_Reg                0x37


#define CMD_TYPE_0_MASTER      3
#define CMD_TYPE_1_MASTER      4
#define CMD_TYPE_2_MASTER      5

#define TYPE_0_LENGTH   1
#define TYPE_1_LENGTH   2
#define TYPE_2_LENGTH   6

#define MAX_BUFFER_SIZE     20

/* MasterTypeX are example buffers initialized in the master, they will be
 * sent by the master to the slave.
 * SlaveTypeX are example buffers initialized in the slave, they will be
 * sent by the slave to the master.
 * */

uint8_t MasterType2 [TYPE_2_LENGTH] = {'F', '4', '1', '9', '2', 'B'};
uint8_t MasterType1 [TYPE_1_LENGTH] = { 8, 9};
uint8_t MasterType0 [TYPE_0_LENGTH] = {0x08};
uint8_t MasterType3 [TYPE_0_LENGTH] = {0x0A};
uint8_t MasterType4 [TYPE_0_LENGTH] = {0x03};


uint8_t SlaveType2 [TYPE_2_LENGTH] = {0};
uint8_t SlaveType1 [TYPE_1_LENGTH] = {0};
uint8_t SlaveType0 [TYPE_0_LENGTH] = {0};

//******************************************************************************
// General I2C State Machine ***************************************************
//******************************************************************************

typedef enum I2C_ModeEnum{
    IDLE_MODE,
    NACK_MODE,
    TX_REG_ADDRESS_MODE,
    RX_REG_ADDRESS_MODE,
    TX_DATA_MODE,
    RX_DATA_MODE,
    SWITCH_TO_RX_MODE,
    SWITHC_TO_TX_MODE,
    TIMEOUT_MODE
} I2C_Mode;


/* Used to track the state of the software state machine*/
I2C_Mode MasterMode = IDLE_MODE;

/* The Register Address/Command to use*/
uint8_t TransmitRegAddr = 0;

/* ReceiveBuffer: Buffer used to receive data in the ISR
 * RXByteCtr: Number of bytes left to receive
 * ReceiveIndex: The index of the next byte to be received in ReceiveBuffer
 * TransmitBuffer: Buffer used to transmit data in the ISR
 * TXByteCtr: Number of bytes left to transfer
 * TransmitIndex: The index of the next byte to be transmitted in TransmitBuffer
 * */
uint8_t ReceiveBuffer[MAX_BUFFER_SIZE] = {0};
uint8_t RXByteCtr = 0;
uint8_t ReceiveIndex = 0;
uint8_t TransmitBuffer[MAX_BUFFER_SIZE] = {0};
uint8_t TXByteCtr = 0;
uint8_t TransmitIndex = 0;

int16_t xf=0;
int16_t yf=0;
int16_t zf=0;

uint8_t Data_rate=0;
uint8_t Data_Res =0;
uint8_t Dev_ID   =0;



/* I2C Write and Read Functions */

/* For slave device with dev_addr, writes the data specified in *reg_data
 *
 * dev_addr: The slave device address.
 *           Example: SLAVE_ADDR
 * reg_addr: The register or command to send to the slave.
 *           Example: CMD_TYPE_0_MASTER
 * *reg_data: The buffer to write
 *           Example: MasterType0
 * count: The length of *reg_data
 *           Example: TYPE_0_LENGTH
 *  */
I2C_Mode I2C_Master_WriteReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t *reg_data, uint8_t count);

/* For slave device with dev_addr, read the data specified in slaves reg_addr.
 * The received data is available in ReceiveBuffer
 *
 * dev_addr: The slave device address.
 *           Example: SLAVE_ADDR
 * reg_addr: The register or command to send to the slave.
 *           Example: CMD_TYPE_0_SLAVE
 * count: The length of data to read
 *           Example: TYPE_0_LENGTH
 *  */
I2C_Mode I2C_Master_ReadReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t count);
void CopyArray(uint8_t *source, uint8_t *dest, uint8_t count);


I2C_Mode I2C_Master_ReadReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t count)
{
    /* Initialize state machine */
    MasterMode = TX_REG_ADDRESS_MODE;
    TransmitRegAddr = reg_addr;
    RXByteCtr = count;
    TXByteCtr = 0;
    ReceiveIndex = 0;
    TransmitIndex = 0;

    /* Initialize slave address and interrupts */
    UCB2I2CSA = dev_addr;
    UCB2IFG &= ~(UCTXIFG + UCRXIFG);       // Clear any pending interrupts
    UCB2IE &= ~UCRXIE;                       // Disable RX interrupt
    UCB2IE |= UCTXIE;                        // Enable TX interrupt

    UCB2CTLW0 |= UCTR + UCTXSTT;             // I2C TX, start condition
    __enable_interrupt();
//    int i=0;
//    for(i=0;i<50;i++);
    __bis_SR_register(LPM0_bits);           // Enter LPM0 w/ interrupts
//    __bis_SR_register(LPM0_bits + GIE);           // Enter LPM0 w/ interrupts
    return MasterMode;

}


I2C_Mode I2C_Master_WriteReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t *reg_data, uint8_t count)
{
    /* Initialize state machine */
    MasterMode = TX_REG_ADDRESS_MODE;
    TransmitRegAddr = reg_addr;

    //Copy register data to TransmitBuffer
    CopyArray(reg_data, TransmitBuffer, count);

    TXByteCtr = count;
    RXByteCtr = 0;
    ReceiveIndex = 0;
    TransmitIndex = 0;

    /* Initialize slave address and interrupts */
    UCB2I2CSA = dev_addr;
    UCB2IFG &= ~(UCTXIFG + UCRXIFG);       // Clear any pending interrupts
    UCB2IE &= ~UCRXIE;                       // Disable RX interrupt
    UCB2IE |= UCTXIE;                        // Enable TX interrupt

    UCB2CTLW0 |= UCTR + UCTXSTT;             // I2C TX, start condition
//    __enable_interrupt();
    __bis_SR_register(LPM0_bits + GIE);           // Enter LPM0 w/ interrupts

    return MasterMode;
}

void CopyArray(uint8_t *source, uint8_t *dest, uint8_t count)
{
    uint8_t copyIndex = 0;
    for (copyIndex = 0; copyIndex < count; copyIndex++)
    {
        dest[copyIndex] = source[copyIndex];
    }
}


//******************************************************************************
// Device Initialization *******************************************************
//******************************************************************************


void initGPIO()
{
    // Configure GPIO
    LED_OUT &= ~(LED0_PIN | LED1_PIN); // P1 setup for LED & reset output
    LED_DIR |= (LED0_PIN | LED1_PIN);

    // I2C pins
    P7SEL0 |= BIT0 | BIT1;
    P7SEL1 &= ~(BIT0 | BIT1);

    // Disable the GPIO power-on default high-impedance mode to activate
    // previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;
}

void initClockTo16MHz()
{
    // Configure one FRAM waitstate as required by the device datasheet for MCLK
    // operation beyond 8MHz _before_ configuring the clock system.
    FRCTL0 = FRCTLPW | NWAITS_1;

    // Clock System Setup
    CSCTL0_H = CSKEY_H;                     // Unlock CS registers
    CSCTL1 = DCOFSEL_0;                     // Set DCO to 1MHz

    // Set SMCLK = MCLK = DCO, ACLK = LFXTCLK (VLOCLK if unavailable)
    CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;

    // Per Device Errata set divider to 4 before changing frequency to
    // prevent out of spec operation from overshoot transient
    CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4;   // Set all corresponding clk sources to divide by 4 for errata
    CSCTL1 = DCOFSEL_4 | DCORSEL;           // Set DCO to 16MHz

    // Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
    __delay_cycles(60);
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;   // Set all dividers to 1 for 16MHz operation
    CSCTL0_H = 0;                           // Lock CS registers
}

void initI2C()
{
    UCB2CTLW0 = UCSWRST;                      // Enable SW reset
    UCB2CTLW0 |= UCMODE_3 | UCMST | UCSSEL__SMCLK | UCSYNC; // I2C master mode, SMCLK
    UCB2BRW = 160;                            // fSCL = SMCLK/160 = ~100kHz
    UCB2I2CSA = SLAVE_ADDR;                   // Slave Address
    UCB2CTLW0 &= ~UCSWRST;                    // Clear SW reset, resume operation
    UCB2IE |= UCNACKIE;
}


//******************************************************************************
// Main ************************************************************************
// Send and receive three messages containing the example commands *************
//******************************************************************************

int main(void) {
    WDTCTL = WDTPW | WDTHOLD;   // Stop watchdog timer
    initClockTo16MHz();
    initGPIO();
    initI2C();
    int i=0;

   I2C_Master_ReadReg(SLAVE_ADDR, CMD_TYPE_0_SLAVE, TYPE_0_LENGTH);
   CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
   for(i=0; i<50;i++);
   Dev_ID=ReceiveBuffer[0];
   for(i=0; i<50;i++);

    I2C_Master_WriteReg(SLAVE_ADDR, Power_CTL, MasterType0, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
//
    I2C_Master_WriteReg(SLAVE_ADDR, Data_Rate, MasterType3, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
//
    I2C_Master_WriteReg(SLAVE_ADDR, Data_Format, MasterType4, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
//

    I2C_Master_ReadReg(SLAVE_ADDR, Data_Rate, TYPE_0_LENGTH);
    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
    Data_rate=ReceiveBuffer[0];
    for(i=0; i<50;i++);

    I2C_Master_ReadReg(SLAVE_ADDR, Data_Format, TYPE_0_LENGTH);
    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
    Data_Res=ReceiveBuffer[0];
    for(i=0; i<50;i++);;
while(1)
{
    I2C_Master_ReadReg(SLAVE_ADDR, X0_Reg, TYPE_1_LENGTH);
    CopyArray(ReceiveBuffer, SlaveType0, TYPE_1_LENGTH);
    for(i=0; i<50;i++);
    uint8_t x0 = ReceiveBuffer[0];
    for(i=0; i<50;i++);

    I2C_Master_ReadReg(SLAVE_ADDR, X1_Reg, TYPE_0_LENGTH);
    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
    uint8_t x1 = ReceiveBuffer[0];
    for(i=0; i<50;i++);

    x1=x1&0x03;
    uint16_t x = (x1 << 8) + x0;
    xf = x;
    if(xf > 511)
    {
     xf = xf - 1024;
    }

    I2C_Master_ReadReg(SLAVE_ADDR, Z0_Reg, TYPE_0_LENGTH);
    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
    uint8_t z0 = ReceiveBuffer[0];
    for(i=0; i<50;i++);

    I2C_Master_ReadReg(SLAVE_ADDR, Z1_Reg, TYPE_0_LENGTH);
    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
    uint8_t z1 = ReceiveBuffer[0];
    for(i=0; i<50;i++);

    z1=z1&0x03;
    uint16_t z = (z1 << 8) + z0;
    zf = z;
    if(zf > 511)
    {
     zf = zf - 1024;
    }

    I2C_Master_ReadReg(SLAVE_ADDR, Y0_Reg, TYPE_0_LENGTH);
    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
    uint8_t y0 = ReceiveBuffer[0];
    for(i=0; i<50;i++);

    I2C_Master_ReadReg(SLAVE_ADDR, Y1_Reg, TYPE_0_LENGTH);
    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
    for(i=0; i<50;i++);
    uint8_t y1 = ReceiveBuffer[0];
    for(i=0; i<50;i++);

    y1=y1&0x03;
    uint16_t y = (y1 << 8) + y0;
    yf = y;
    if(yf > 511)
    {
     yf = yf - 1024;
    }
    for(i=0; i<50;i++);
    printf("X: %d\n",xf);
    printf("Y: %d\n",yf);
    printf("Z: %d\n",zf);
    __delay_cycles(100);

}

//    I2C_Master_ReadReg(SLAVE_ADDR, CMD_TYPE_0_SLAVE, TYPE_0_LENGTH);
//    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
//
//    I2C_Master_WriteReg(SLAVE_ADDR, CMD_TYPE_0_MASTER, MasterType0, TYPE_0_LENGTH);
//    I2C_Master_WriteReg(SLAVE_ADDR, CMD_TYPE_1_MASTER, MasterType1, TYPE_1_LENGTH);
//    I2C_Master_WriteReg(SLAVE_ADDR, CMD_TYPE_2_MASTER, MasterType2, TYPE_2_LENGTH);
//
//    I2C_Master_ReadReg(SLAVE_ADDR, CMD_TYPE_0_SLAVE, TYPE_0_LENGTH);
//    CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
//
//    I2C_Master_ReadReg(SLAVE_ADDR, CMD_TYPE_1_SLAVE, TYPE_1_LENGTH);
//    CopyArray(ReceiveBuffer, SlaveType1, TYPE_1_LENGTH);
//
//    I2C_Master_ReadReg(SLAVE_ADDR, CMD_TYPE_2_SLAVE, TYPE_2_LENGTH);
//    CopyArray(ReceiveBuffer, SlaveType2, TYPE_2_LENGTH);

    __bis_SR_register(LPM0_bits + GIE);
    return 0;
}


//******************************************************************************
// I2C Interrupt ***************************************************************
//******************************************************************************

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B2_VECTOR
__interrupt void USCI_B2_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B2_VECTOR))) USCI_B2_ISR (void)
#else
#error Compiler not supported!
#endif
{
  //Must read from UCB2RXBUF
  uint8_t rx_val = 0;
  switch(__even_in_range(UCB2IV, USCI_I2C_UCBIT9IFG))
  {
    case USCI_NONE:          break;         // Vector 0: No interrupts
    case USCI_I2C_UCALIFG:   break;         // Vector 2: ALIFG
    case USCI_I2C_UCNACKIFG:                // Vector 4: NACKIFG
      break;
    case USCI_I2C_UCSTTIFG:  break;         // Vector 6: STTIFG
    case USCI_I2C_UCSTPIFG:  break;         // Vector 8: STPIFG
    case USCI_I2C_UCRXIFG3:  break;         // Vector 10: RXIFG3
    case USCI_I2C_UCTXIFG3:  break;         // Vector 12: TXIFG3
    case USCI_I2C_UCRXIFG2:  break;         // Vector 14: RXIFG2
    case USCI_I2C_UCTXIFG2:  break;         // Vector 16: TXIFG2
    case USCI_I2C_UCRXIFG1:  break;         // Vector 18: RXIFG1
    case USCI_I2C_UCTXIFG1:  break;         // Vector 20: TXIFG1
    case USCI_I2C_UCRXIFG0:                 // Vector 22: RXIFG0
        rx_val = UCB2RXBUF;
        if (RXByteCtr)
        {
          ReceiveBuffer[ReceiveIndex++] = rx_val;
          RXByteCtr--;
        }

        if (RXByteCtr == 1)
        {
          UCB2CTLW0 |= UCTXSTP;
        }
        else if (RXByteCtr == 0)
        {
          UCB2IE &= ~UCRXIE;
          MasterMode = IDLE_MODE;
          __bic_SR_register_on_exit(CPUOFF);      // Exit LPM0
        }
        break;
    case USCI_I2C_UCTXIFG0:                 // Vector 24: TXIFG0
        switch (MasterMode)
        {
          case TX_REG_ADDRESS_MODE:
              UCB2TXBUF = TransmitRegAddr;
              if (RXByteCtr)
                  MasterMode = SWITCH_TO_RX_MODE;   // Need to start receiving now
              else
                  MasterMode = TX_DATA_MODE;        // Continue to transmision with the data in Transmit Buffer
              break;

          case SWITCH_TO_RX_MODE:
              UCB2IE |= UCRXIE;              // Enable RX interrupt
              UCB2IE &= ~UCTXIE;             // Disable TX interrupt
              UCB2CTLW0 &= ~UCTR;            // Switch to receiver
              MasterMode = RX_DATA_MODE;    // State state is to receive data
              UCB2CTLW0 |= UCTXSTT;          // Send repeated start
              if (RXByteCtr == 1)
              {
                  //Must send stop since this is the N-1 byte
                  while((UCB2CTLW0 & UCTXSTT));
                  UCB2CTLW0 |= UCTXSTP;      // Send stop condition
              }
              break;

          case TX_DATA_MODE:
              if (TXByteCtr)
              {
                  UCB2TXBUF = TransmitBuffer[TransmitIndex++];
                  TXByteCtr--;
              }
              else
              {
                  //Done with transmission
                  UCB2CTLW0 |= UCTXSTP;     // Send stop condition
                  MasterMode = IDLE_MODE;
                  UCB2IE &= ~UCTXIE;                       // disable TX interrupt
                  __bic_SR_register_on_exit(CPUOFF);      // Exit LPM0
              }
              break;

          default:
              __no_operation();
              break;
        }
        break;
    default: break;
  }
}

This looks OK as far as it goes. How do you combine the two?

Also: how do you tell that the timer interrupt isn't happening? A breakpoint in the ISR? Or some external indicator?

First i tried with the breakpoint and then i tried by enabling a Led under the interrupt routine. I guess the while entering the LPM in the i2c transaction it disables the timer interrupt or spin lock that you've mentioned earlier

What does your combined main (the one that fails) look like? I notice that your timer example enables interrupts (GIE) right at the beginning, but the I2C example doesn't enable GIE until the first I2C operation. I'm wondering what the resulting (failing) code does.

This is my combined code. In this one the timer interrupt is not triggering at all

#include <msp430.h> 
#include <mlx90614.h>
#include <ADXL345.h>
#include <i2c.h>
#include <stdint.h>
#include <stdio.h>

#include <Timer.h>

/**
 * main.c
 */
#define Clock_div 160

typedef enum sys_mode{
    Idle_mode,
    Accel_mode,
    Pox_mode,
    Temp_mode
} sys_mode;

sys_mode Mode =  Accel_mode;


int i=0;

uint8_t ADXL345_Dev_ID=0;
uint8_t Data_rate=0;
uint8_t Data_Res=0;



uint64_t Temp_Dev_Address=0;
int Temperature=0;



int16_t xf=0;
int16_t yf=0;
int16_t zf=0;

int time_count=0;

volatile uint32_t millis=0;
uint8_t se=0;

void  i2c_setup()
{
    initClockTo16MHz();
    initGPIO();
}
void init_ADXL345()
{
    initI2C(ADXL_Address,Clock_div);
    read_id(ADXL345_Dev_ID);
    Reg_config();
}

void init_MLX90614()
{
  Temp_Dev_Address=temp_read_id();
  for(i=0; i<50;i++);
}

int main(void)
{
	WDTCTL = WDTPW | WDTHOLD;	// stop watchdog timer
    P1DIR |= BIT0;
    P1OUT |= BIT0;


	i2c_setup();
	init_ADXL345();
	Timer_intialize();
while(1)
{

	if(Mode==Accel_mode)
	{
	     xf= getx();
	     yf=gety();
	     zf=getz();
	     time_count++;
	     time(millis);
	     se=timestamp_obj.secs;
//	     UART_Int("x:",xf);
//	     UART_Int("y:",yf);
//	     UART_Int("z:",zf);
//	     printf("X:%d\n",xf);
//	     printf("Y:%d\n",yf);
//	     printf("Z:%d\n",zf);
	     if(time_count>=10)
	     {
	      time_count=0;
	      Mode=Temp_mode;
	     }
	     else
	     {
	         Mode=Accel_mode;
	     }
	}
	if (Mode==Temp_mode)
	{
	    Temperature=readobject();
	   // UART_Int("T:",Temperature);
	   // printf("%d\n",Temperature);
	    time_count++;
	    if(time_count>=10)
	    {
	        time_count=0;
	        Mode=Idle_mode;
	    }
	}
}
	return 0;
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B2_VECTOR
__interrupt void USCI_B2_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B2_VECTOR))) USCI_B2_ISR (void)
#else
#error Compiler not supported!
#endif
{
  //Must read from UCB2RXBUF
  uint8_t rx_val = 0;
  switch(__even_in_range(UCB2IV, USCI_I2C_UCBIT9IFG))
  {
    case USCI_NONE:          break;         // Vector 0: No interrupts
    case USCI_I2C_UCALIFG:   break;         // Vector 2: ALIFG
    case USCI_I2C_UCNACKIFG:                // Vector 4: NACKIFG
      break;
    case USCI_I2C_UCSTTIFG:  break;         // Vector 6: STTIFG
    case USCI_I2C_UCSTPIFG:  break;         // Vector 8: STPIFG
    case USCI_I2C_UCRXIFG3:  break;         // Vector 10: RXIFG3
    case USCI_I2C_UCTXIFG3:  break;         // Vector 12: TXIFG3
    case USCI_I2C_UCRXIFG2:  break;         // Vector 14: RXIFG2
    case USCI_I2C_UCTXIFG2:  break;         // Vector 16: TXIFG2
    case USCI_I2C_UCRXIFG1:  break;         // Vector 18: RXIFG1
    case USCI_I2C_UCTXIFG1:  break;         // Vector 20: TXIFG1
    case USCI_I2C_UCRXIFG0:                 // Vector 22: RXIFG0
        rx_val = UCB2RXBUF;
        if (RXByteCtr)
        {
          ReceiveBuffer[ReceiveIndex++] = rx_val;
          RXByteCtr--;
        }

        if (RXByteCtr == 1)
        {
          UCB2CTLW0 |= UCTXSTP;
        }
        else if (RXByteCtr == 0)
        {
          UCB2IE &= ~UCRXIE;
          MasterMode = IDLE_MODE;
          __bic_SR_register_on_exit(CPUOFF);      // Exit LPM0
        }
        break;
    case USCI_I2C_UCTXIFG0:                 // Vector 24: TXIFG0
        switch (MasterMode)
        {
          case TX_REG_ADDRESS_MODE:
              UCB2TXBUF = TransmitRegAddr;
              if (RXByteCtr)
                  MasterMode = SWITCH_TO_RX_MODE;   // Need to start receiving now
              else
                  MasterMode = TX_DATA_MODE;        // Continue to transmision with the data in Transmit Buffer
              break;

          case SWITCH_TO_RX_MODE:
              UCB2IE |= UCRXIE;              // Enable RX interrupt
              UCB2IE &= ~UCTXIE;             // Disable TX interrupt
              UCB2CTLW0 &= ~UCTR;            // Switch to receiver
              MasterMode = RX_DATA_MODE;    // State state is to receive data
              UCB2CTLW0 |= UCTXSTT;          // Send repeated start
              if (RXByteCtr == 1)
              {
                  //Must send stop since this is the N-1 byte
                  while((UCB2CTLW0 & UCTXSTT));
                  UCB2CTLW0 |= UCTXSTP;      // Send stop condition
              }
              break;

          case TX_DATA_MODE:
              if (TXByteCtr)
              {
                  UCB2TXBUF = TransmitBuffer[TransmitIndex++];
                  TXByteCtr--;
              }
              else
              {
                  //Done with transmission
                  UCB2CTLW0 |= UCTXSTP;     // Send stop condition
                  MasterMode = IDLE_MODE;
                  UCB2IE &= ~UCTXIE;                       // disable TX interrupt
                  __bic_SR_register_on_exit(CPUOFF);      // Exit LPM0
              }
              break;

          default:
              __no_operation();
              break;
        }
        break;
    default: break;
  }
}

// Timer0_B0 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=TIMER0_B1_VECTOR

__interrupt void TIMER0_B1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER0_B1_VECTOR))) TIMER0_B1_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch(__even_in_range(TB0IV, TBIV__TBIFG))
    {
        case TBIV__NONE:    break;          // No interrupt
        case TBIV__TBCCR1: break;           // TB0CCR1 interrupt
        case TBIV__TBCCR2: break;           // TB0CCR2 interrupt
        case TBIV__TBCCR3: break;           // TB0CCR3 interrupt
        case TBIV__TBCCR4: break;           // TB0CCR4 interrupt
        case TBIV__TBCCR5: break;           // TB0CCR5 interrupt
        case TBIV__TBCCR6: break;           // TB0CCR6 interrupt
        case TBIV__TBIFG:                   // overflow
            millis=millis+2;
            P1OUT ^= BIT0;
            break;
        default: break;
    }
}

First principles: 

1) if you pause the program in the debugger, where are you executing?

2) In the debugger Registers view, under "CPU registers" (top line), what is the value of SR? In particular, is GIE=1?

3) Under TIMER_B0 (further down), what is the value of TB0CTL? In particular, are both TBIE=1 and TBIFG=1?

If GIE=1, TBIE=1, and TBIFG=1, then we expect the ISR will be called; if not, that points one direction. If one of these is =0, that points in a different direction.

Hey bruce i have checked it  and these are status of the bits

GIE=0, TBIE=1, and TBIFG=0

1) if you pause the program in the debugger, where are you executing? 

2) What is the value of TB0CTL? [Now we're interested in TBSSEL and MC, to see whether the timer is running. We're still interested in TBIE and TBIFG.]