Hi,
Question 1
https://www.ti.com/lit/ds/symlink/msp430f5132.pdf
(1) is described as a Note in the table below in the above URL.
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・ Table 6-11. TD0 Signal Connections
(1) Pins P1.6 for TD0.0, P1.7 for TD0.1, and P2.0 for TD0.2 are optimized for matching.
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What exactly does "optimized for matching" mean?
Considering the wiring delay etc., does it mean that it is necessary to assign to the described terminals in order to realize "256-MHz (4-ns) resolution"?
Question 2
I have a question about using the "Port Mapping Controller".
PM_TD0.0, PM_TD0.1, PM_TD0.2, PM_TD1.0, PM_TD1.1, PM_TD1.2 for terminals other than the combination of P1.6, P1.7, P2.0, P2.1, P2.2, P2.3 Are there any restrictions if I assign?
Thanks,
Koki