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MSP430FR2676: SPI master maximum feUSCI datasheet specification

Nuno Romao
Prodigy 200 points
Part Number: MSP430FR2676


The datasheet for the MSPFR2676 says the maximum "eUSCI input clock frequency", feUSCI, for SPI master mode is 8 MHz. Does that mean that the maximum SMCLK frequency is 8 MHz for SPI master mode or is this the maximum frequency of the generated bit clock? For these devices the maximum specified SMCLK is 16 MHz, so it would be odd if this module could only operate at up to 8 MHz maximum SMCLK frequency in SPI master mode. In other modes, like UART mode, feUSCI has a maximum of 16 MHz for the same module. Most other FRxxx devices have feUSCI specified as 16 MHz for SPI master mode.

  • 0
    TI__Mastermind 26860 points

    Hi Nuno,

    The input clock frequency shouldn't be confused with operation frequency for the other devices. The reason that SPI is set to 8MHz is a hardware limitation as that clock is the direct SPI clock for the system. For I2C and UART they actually have 2 different frequencies , the clock input that they take for running the module on the MCU side then the clock used for interacting with data (SCL Clock for I2C and BitClock  for UART). The niche with SPI is is uses 1 clock for both of these. 

    Were you just curious as to why they were different or did you want to maximize the throughput of data for the SPI? If you're wanting to maximize throughput, there's some other considerations, like how you interact with the data and your peripherals used. 

    Regards,

    Luke

  • 0 in reply to Luke Ledbetter
    Prodigy 200 points

    Thanks for the response Luke. What I want to know is what is feUSCI? After looking into this a bit more I see that BRCLK, which is the clock source for the bit clock generator, can be sourced externally (UCSSELx = 1). I think feUSCI is the frequency of the external clock and this is the specification for the maximum external clock frequency. I would like confirmation of that. I am not going to use an external clock, but feUSCI is not defined anywhere in the datasheet as to what it is. I want to run SMCLK at 16 MHz and the SPI bit clock as high as possible.

  • 0
    Prodigy 200 points

    Just to clarify what I want to know:

    • Is feUSCI the same clock as SMCLK or is it the external clock source when UCSSELx = 1?
    • Can I run SMCLK at 16 MHz if I'm using the USCI module in master SPI mode?
  • 0 in reply to Nuno Romao
    TI__Mastermind 26860 points

    feUSCI is the frequency of the eUSCI, from the Datasheet when UCSSEL is 1 it would use the ACLK. (see below image) for the external clock you would want UCSSEL = 0 and for SMCLK UCSSEL = 2 or 3

    You should max the SMCLK at 8MHz if you want it to drive SPI. You can still run the MCLK at the 16MHz or use the ACLK to run SPI.

  • 0 in reply to Luke Ledbetter
    Prodigy 200 points

    UCSSEL is the BRCLK clock mux selector, it's not the module clock, which is always SMCLK. From the user manual:

    It looks like the device datasheet has different clocks for UCSSEL 00 and 01, but that's not important.

    If feUSCI is selected by UCSSEL as you say, feUSCI is the frequency of BRCLK, not the module clock.

  • +1 in reply to Nuno Romao
    TI__Mastermind 26860 points

    ACLK and SMCLK are the clocks that control peripherals, MCLK is the main CPU clock for the whole MCU. For this specific SPI module, you can select between those 4 inputs on the mux for the clock (N/A, Device Specific [ACLK for this device], SMCLK, and SMCLK). When UCSSEL = 1 it would feed the ACLK for BRCLK. So it is not always SMCLK but can also be the ACLK.

    UCSSEL selects the clock source for the module

    As I stated initially the module clock is the same here so BRCLK = the frequency of the eUSCI. You can tune the end bit clock with that prescaler/divider, but due to hardware limitations the max is 8MHz for initial clock input.

    Below explains further about the BRCLK going to the bit clock.

    I hope this helps clarify

    Regards,

    Luke

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