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XT2 External Clock

Sean Kocher
Prodigy 20 points

Other Parts Discussed in Thread: MSP430F5529

Hello!

I am trying to get a 25Mhz external clock to power a msp430f5529, however we are experiencing an odd result. Using stock code from the core libraries, plus upping the vcore voltage to level 3, as well as the XDRIVE level. We then pinout the MCLK and SMCLK so that we can scope the result. We are getting our 25Mhz oscillation, but it is more of a triangle wave.

http://i.imgur.com/pWm2A.jpg

 

At first I thought this was because XT2BYPASS was enabled, but I did not find it anywhere in the code. I also tried a second scope, so its not that. Somebody suggested that getting this result shouldn't be possible, so I am not quite sure whats going on. Possibly has something to do with capacitor values, but I'm not sure; I'm not an EE.

 

Has anybody experienced something like this before? Thanks!

  • 0
    Guru 227245 points

    Yes, there was anothe rthread about this. Check the device datasheet, the digital outputs section. The rise and fall times (slew rates) of the digital output drivers are on their limits on 25MHz. So the rising edge more or less meets the falling edge on this speed.

    teh datasheet says: 'the output reaches at least 10% and 90% VCC at the specified toggle frequency". This means, on 25MHz, the fallign edge will go at least down to 10% VCC (not settle at 0%!) before the rising edge begins (and reaches at least 90%VCC).Specified for 20pF load (calculate the impedance on 25MHz yourself). That's a triangle in worst case. But even in best case no square.

     

  • 0 in reply to Jens-Michael Gross
    Prodigy 20 points

    Thanks for the response!

    We noticed that things (ex. UART -- sourcing SMCLK which had been divided down to 3.1Mhz) were locking up when running MCLK without a divider, but everything works fine when we divide it down to 12.5MHz. Does this sound about right? I'm surprised that we can't run it at the full speed without locking things, but maybe I misunderstood the specs and the 25MHz doesn't mean the main system can run at that speed (or we should have gotten a 20MHz and not pushed the limit). Either way I think we can settle for now with 12.5MHz clock. Thanks again!

  • 0 in reply to Sean Kocher
    Guru 227245 points

    The maximum bit clock for the UART is 1MHz. However, the internal clock can be as much as 25MHz.
    Having a triangle-like output of a 25MHz signal does not affect internal operations or the UART ouput. It will, however, affect communication with external devices using SPI at full clock speed. Here the question is how the external devices cna deal with the signal. Teh datasheet might define a minimum time after reaching the positive trigger level before reaching the negative trigger level again. This must be calculated if you really want to run on maximum.
    There shouldn't, however, be any problem clocking the cpu core with 25MHz, if VCC is okay, VCore is set properly, and the 25MHz are not (even temporarily) exceeded (which will happen if you use the DCO with modulation, as the 25MHz here are just an average, so sometimes higher). The maximum safe frequency here is 23.4MHz (worst case)<br>

    What is your clock source? A 25MHz crystal? Or an external oscillator? How is it connected then?

    How do you initialize things?

    And what exactly do you mean with 'things were locking up'?

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