MPS430 op-codes, documentation, and other questions

My understanding of the “Jumps instruction” for MSP430 is as follows.

Bit-15, 14, 13 are the “op-code”.

    For all “Jumps instruction”, they must be 0, 0, 1.

Bit-12, 11, 10 are the “C” (or condition) of the Jump.

   For JZ, they are 0, 0, 0.

   For JNZ, they are 0, 0, 1.

   For JC, they are 0, 1, 0.

   For JNC, they are 0, 1, 1.

   For JN, they are 1, 0, 0.

   For JGE, they are 1, 0, 1.

   For JL, they are 1, 1, 0.

   For JMP, they are 1, 1, 1.

Bit-9, 8, ..., 0 are the 10-bit PC offset (actually, offset/2).

My understanding of the address mode for MSP430 is as follows.

For the Destination Address of a Double-Operand, there are only two address modes, namely (a) Register-mode and (b) Indexed-mode.

For the Source Address of a Double-operand, or the Address of a Single-operand, there are two additional address modes, namely (c) Indirect-mode and (d) Indirect-auto-increment-mode.

But when the register is R0/PC, R1/SP, R2/SR/CG1, or R3/CG2, the address modes behave differently (the “orthogonal architectural” is gone with the wind).

Specifically, R0/PC in Indirect-auto-increment mode is called (e) Immediate-mode.
R0/PC in Indexed-mode is called (f) Symbolic-mode.
R2/SR in Indexed-mode is called (g) Absolute-mode.

“When I use a word,” Humpty Dumpty said, in a rather a scornful tone, “it means just what I choose it to mean—neither more nor less.” -- Lewis Carroll's Through the Looking-Glass

Thanks, those answers help clarify.

To follow up:  did either of you figure this out from the "MPS430 Family" document, or is there a better document that describes the processor instruction set and addressing modes?

Since posting, I found that Wikipedia seems to have a clearer explanation of the instruction set and opcodes.  But I'd much prefer to find good, clear, accurate TI documents to work from if they exist.

I'm still not clear on "Symbolic Mode" and what address the offset is added to.

Regards,

-SB

s b said:

... But I'd much prefer to find good, clear, accurate TI documents to work from if they exist. . . .

I prefer that too, but no luck so far.

s b said:

...I'm still not clear on "Symbolic Mode" and what address the offset is added to.

The Assembler&Linker will calculate the PC offset of the Symbol and put that offset into the Object Code. When that Object Code is executed, the CPU will use PC in Indexed-mode with that offset (undoing what Assembler&Linker did).

For example: Assume that the RAM at 0234 has a Symbolic name "bar", and you want to zero it. Using Symbolic-mode, you write "mov.b #0,bar". The Assembler&Linker generates an instruction at F800-F803: 43C0 0A32 (where 0A32=0234-F802 is the PC offset of 0234). During execution, the effective address of the destination is F802+0A32=0234 (which has the Symbolic name "bar").

s b said:

Why is it named "MSP430x2xx"

All families share certain characteristica. So do have all 1x devices a basic clock module, all 2x have a basic clock module +, the 4x have a FLL+ clock module and the 5x/6x devices an universal clock system.

The different user guides describe the common characteristica of all devices in one family, as well as all hardware that is available in one (but not all) devices of a family.

E.g. each 3x member may have one or more USI or USCI modules (or none at all), but the 2x family USCI module differs from teh 5x/6x family USCI module. (and the 1x family has USART modules).

Which specific hardwar eof this collection is available for a particular family member is written into the device datasheet. These datasheets may be for a sub-group of MSPs which are mostly identical in terms of operation conditions and other specs, but may have a different number of pins and therefore ports and/or ADC inputs, or different amount of ram or flash. E.g. the 5438 and the 546 ar eidenical except for 64k of additional flash in teh 38 which is not in the 36..
The 5437 and 38, however, have the same amount of flash, but the 37 has only 2 instead of 4 USCI modules and 80 instead of 100 pins. The 35 then is like the 37 but again with 64k less flash. All of them share the same datasheet.
The 54xxA, however, ar eof th esame family, but have different specs (higher operating frequency, additional REF module and different settings for the voltage supervisor etc.), so they have their own datasheet, but share the same users guide, since the modules are the same and so are the register descriptions etc.

One could melt all this into individual datasheets for each and every MSP, but this would result in a hughe bunch of large datasheets, adn while it would make it easier to work on one device, it would also make it way more difficult to move between devices.
And the effort for keeping them all up-to-date would be enormous, including the increased chance for errors.

Well, an MSP is no TTL device.

s b said:

How do you find the actual instruction op codes

OCY has explained the jumps. The arithmetical instructions are assembled by

• operation (AND, OR etc.)
• source addressing mode (register, indirect etc.)
• source register (for register or indirect mdoes)
• destination address mode
• destination register
• byte/word mode flag

See fig. 5-22 for those double-operand instructions (5x users guide, 4.5.1.1 in 2x users guide)
The operation is determined by the upper 4 bits (12 of the 16 combinations)

The jumps are in the 2000-3f00 range and include the 10 bit signed offset in words, as well as the condition (compared against the status register)

Single-operand instructions such as RRC or push do not have source register and addressing mode, so there are 5 more bits for the instruction

And then there are a few special operations which don't fit into any scheme, such as RET and RETI.

The new MSP430X instrucitons (with 20 bit operands)fille hte previously unused ares on 0xxx and 1400-17ff (address mode operations, which work only register/register except for the MOVA) and the also unused gap in 1800-1fff is filled by the extension word that precedes any 430X instruction and contains the mising 4 bits for the 20 bit source and destination operands.

s b said:

It would be helpful for example if each instruction listed its op code in the main instruction reference, or if there were at least a simple list of op codes corresponding to the instructions.

s b said:

For each mode, it shows an example of "Assembler Code" and something called "Content of ROM"

s b said:

But the documentation for this mode is not clear.  It describes the source address as (contents of PC + X) and the destination address as (contents of PC + Y), but the example seems to indicate the source address as (contents of PC + 1 + X) and the destination address as (contents of PC + 2 + Y).

However, if you don't plan to write an assembler on your own, just use the mnemonics and all is done for you.

It's all in the faily users guides.

However, it sometime shelps to look into the other families users guides (there aren't that many, only 1x, 2x, 4x and 5x/6x)
Sometimes, the newer ones have a more detailed or straightened descriptions which did not make it (yet) into the 'older' family user guides.

Did you ever try to write a documentation? It's not an easy task, and the most hated one for most engineers. (and those who do not hate it or are explicitely hired to do it, are usually no engineers, so there's an informational gap)

Thanks for the good explanations.  I am looking at this as an assembler writer to try to really understand how the machine instructions work.

I agree, it's darn hard to write good documentation, especially for something as complex as these processors.  IBM did quite a good job for the original IBM PC.  The MSP430 docs are a good start but seem leave out critical info, perhaps assumed to be common knowledge to microcontroller experts.  (I have written a ton of documentation and  work at addressing my own complaints, and it isn't easy.  I believe documents really have to be "alive" and incrementally improved based on user feedback).

For example, it should be explicitly documented how and when the PC is incremented during instruction processing, using an algorithm.  You explained it, but without that knowledge, (PC + X) is ambiguous.

To summarize using Symbolic Mode as an example, it seems then that at the beginning of instruction execution, the PC points to the instruction word.  If an additional extension word is needed for a src operand, the PC is automatically incremented to fetch that word.  If the addressing mode involves the PC, such as "Symbolic" mode, then the current PC value is added to the extension word contents to get the address of the operand.  If an additional extension word is needed for the dest operand, the PC is incremented again to fetch the next extension word.  If it is also "Symbolic" mode, the current PC value is added to the extension word contends to get the address of the dest operand.  After the instruction operation is performed (or is it before???), the PC is incremented again automatically to fetch the next instruction, unless the last instruction was a branch instruction of some sort.

I'm still a little confused about the nomenclature "@PC+" as used to describe the "Immediate Addressing Mode".  "@Rn+" seems clear to me -- use the contents of Rn as an operand address, then increment the register contents.  The problem I have with "@PC+" is that the PC is automatically incremented as part of fetching an extension word, so does the "+" cause an additional increment???

It would be helpful for example if each instruction listed its op code in the main instruction reference, or if there were at least a simple list of op codes corresponding to the instructions.

What throws me off with the "Figure 3-20 Core Instruction Map" in section 3.4.5 is that the jump instructions have codes like 20xx, 24xx, etc.  This implies 8-bit opcodes, but the jump instruction layout in Figure 3-11, section 3.4.3 shows a 3-bit opcode and a 3 bit "C" field.  From Wikipedia I see that the "C" field (unexplained in the TI Doc) is a "condition" field and is really part of the op-code, so we have a 6-bit opcode, which still doesn't correspond to the 8-bit opcodes implied by "Core Instruction Map".   It's little peculiarities like that which make the documentation an exhausting puzzle to be solved rather than an efficient, enabling tool for productive work.

I appreciate all the input and maybe can use a PDF editing tool to augment the TI doc with expanded explanations for my use.

Regards,

-SB

s b said:

If it is also "Symbolic" mode, the current PC value is added to the extension word contends to get the address of the dest operand.

s b said:

is that the PC is automatically incremented as part of fetching an extension word, so does the "+" cause an additional increment???

s b said:

What throws me off with the "Figure 3-20 Core Instruction Map" in section 3.4.5 is that the jump instructions have codes like 20xx, 24xx, etc.

001000xxxxxxxxxx to 001111xxxxxxxxxx

or more precisely:

001 yyy xxxxxxxxxx where 001 is the 'jump opcode' and 'yyy' is the condition and 'x' the signed offset in words.

You never worked with a spark? There the MSB determines whether it is a call instruction (with 31 bit address in words)  or anything else.

s b said:

so we have a 6-bit opcode, which still doesn't correspond to the 8-bit opcodes implied by "Core Instruction Map"

the notation with hex digits dosen't allow the listing of insignificant half-nibbles. And a complete 256x256 table wouldn't help anyone :)

However, the assembler and linker know how to build the opcodes from the mnemonics. So unless you want to write one of them (or debug them)...

Thanks for those explanations that dig under the surface, it's getting clearer.

However, the microcode will always use the @PC+ for any code or operand fetch

I'm still not clear on the nomenclature "@PC+".  What exactly does it mean?  If you are hand-assembling machine code (or writing an assembler), it seems you need to know the details of the PC state during instruction processing in order to put the correct address offsets in the extra words.

is that the PC is automatically incremented as part of fetching an extension word, so does the "+" cause an additional increment???

I was using the term "extension word" like it's used in Wikipedia ("Instructions are 16 bits, followed by up to two 16-bit extension words"); so I really was just asking about how the PC value is referenced during basic MSP430 instruction processing -- which you have answered, although it would be good to have an exact algorithm to refer to.

What throws me off with the "Figure 3-20 Core Instruction Map" in section 3.4.5 is that the jump instructions have codes like 20xx, 24xx, etc.

001000xxxxxxxxxx to 001111xxxxxxxxxx

or more precisely:

001 yyy xxxxxxxxxx where 001 is the 'jump opcode' and 'yyy' is the condition and 'x' the signed offset in words.

You never worked with a spark? There the MSB determines whether it is a call instruction (with 31 bit address in words)  or anything else.

[/quote]

Your explanation is good.  The "core map" (could they be more cryptic???) seems imprecise.

so we have a 6-bit opcode, which still doesn't correspond to the 8-bit opcodes implied by "Core Instruction Map"

the notation with hex digits dosen't allow the listing of insignificant half-nibbles. And a complete 256x256 table wouldn't help anyone :)

However, the assembler and linker know how to build the opcodes from the mnemonics. So unless you want to write one of them (or debug them)...

[/quote]

I like the way Wikipedia http://en.wikipedia.org/wiki/TI_MSP430 shows the instruction set - seems totally clear as a bell.

**** Some new questions:

1.  Orgthogonality Question -  If you look at the SWBP instruction, the B/W field is declared as "0".  What would happen if you put a "1" in that field?

Likewise, the RETI instruction has "00" for the As field and "0000" for the register field.  What would happen if other values were in those fields?

2.  I notice that there is no instruction to rotate bits more than one bit location at a time.  I assume you just need to repeat the instruction for the number of bit places you want to rotate the bits.  Does this tend to eat up a lot of code memory in typical applications?  Or are bit rotations fairly rare or confined to subroutines like multipliers?  Just wondering about the choice to limit the rotate instructions.

-SB

s b said:

I'm still not clear on the nomenclature "@PC+"

However, an operation like

mov @PC+,R15 will probably skip the next instruction, since the fetch of the source operand will increment PC before the next instruction is fetched.

s b said:

it seems you need to know the details of the PC state during instruction processing in order to put the correct address offsets in the extra words.

s b said:

I like the way Wikipedia http://en.wikipedia.org/wiki/TI_MSP430 shows the instruction set - seems totally clear as a bell.

s b said:

If you look at the SWBP instruction, the B/W field is declared as "0".  What would happen if you put a "1" in that field?

Same for the call. A call with a byte operand wouldn't make much sense, there is usually no area where you can/may fetch instructions from in the range from 0x0000 to 0x00ff. And since any immediate parameter will take 16 bit even if only the lower 8 are used, this make snot much sense.

s b said:

RETI instruction has "00" for the As field and "0000" for the register field.  What would happen if other values were in those fields

There were several such opcodes on the old C64's 6510 processor. Some were simply not doing anything, some were crashing th emachine and some did something good, like combining two unrelated normal instructions into one, saving one instruction and one clock cycle. Soemtimes used in heavily optimized loops (such as for compression/decompression or data transfer). Side products of a shrinked/optimized microcode.

s b said:

I notice that there is no instruction to rotate bits more than one bit location at a time.

s b said:

I assume you just need to repeat the instruction for the number of bit places you want to rotate the bits.

s b said:

Just wondering about the choice to limit the rotate instructions

Thanks again.  There is more to these processors than meets the eye, as they say.  I'm sure more questions will come up as I try to program the MSP430G2231.

1.  Can you give a detailed breakdown of the difference between:

mov @PC+,R15

and

move @PC, R15

for example?

 2.  RRUM - ok, I see in the extended instruction set.

Do the rotate instructions do a true rotate, or are they doing a shift and padding with zeros on the trailing end?

BTW: how did you learn the inside details about the MSP430?

Regards,

-SB

s b said:

mov @PC+,R15
and
move @PC, R15

s b said:

Do the rotate instructions do a true rotate, or are they doing a shift and padding with zeros on the trailing end

However, a multiple-bit rol with through carry doesn't make much sense (where should the additional carry bits come from? From a different word or from itself?). However, teh nth bit that is shifted out is shifted to the carry, for what it is worth.
For the single-bit operations, there are some more variations, which rol with carry.(RLCX? etc.)

s b said:

how did you learn the inside details about the MSP430

There are four, arithmetical and logical rotates. IIRC, logical is a shift while arithmetical uses sign extension.The detailed instruction description (far below the isntruciton table in the users guide) has nice diagrams. Few people ever bother to scroll down that many pages without an entry in the bookarkstree :)

You're right, I missed those diagrams -- the info is there.

Would you confirm which document you are referencing?  I don't see an IIRC anywhere in the doc I'm reading (MSP430x2xx Family Users Guide).

(For the most part I'm ignoring the MSP430x "extended" instructions in my questions because I don't expect to be using a processor that supports them for now.)

Here is an interesting note in the docs about the RLA instruction:

 

Note: RLA Substitution

The assembler does not recognize the instruction:

RLA @R5+, RLA.B @R5+, or RLA(.B) @R5

It must be substituted by:

ADD @R5+,−2(R5) ADD.B @R5+,−1(R5) or ADD(.B) @R5

Makes me realize you have to really be on your toes working with these instructions!

(It also highlights the curious relationship of the assembly language definition to the machine instructions.  If TI is defining the assembly language along with the processor, why can't it include that substitution as part of the assembly language!  Especially since RLA is an emulated instruction anyway!  The above note sounds more like it belongs in the errata, not in the processor guide!)

I don't quite understand how "RLA(.B) @R5" translates to "ADD(.B) @R5"  because I don't see an "ADD" syntax with a single operand.

The other substitutions are interesting because they directly relate to our previous discussion about when registers are incremented.  It appears that the R5 register is incremented right after the operand is fetched, in the middle of the instruction, so the destination must be indexed back a byte or word in order to add the value to itself.

Another Question:  What exactly is the meaning/purpose of the "@" nomenclature, since it seems to only apply to source operands?  Is it equivalent to "0(Rx)", or is there some other power it has?

Regards,

-SB

s b said:

I don't see an IIRC anywhere in the doc I'm reading

s b said:

Here is an interesting note in the docs about the RLA instruction

The problem with ALL apparently one-operand instructions which are emulated with two-operand instrucitons is that you give only one parameter and addressing mode for source and destination, yet auto increment mode is only available/valid for source.

s b said:

I don't quite understand how "RLA(.B) @R5" translates to "ADD(.B) @R5" 

s b said:

Makes me realize you have to really be on your toes working with these instructions

However, I think, that this erratum is  rather based on the assenbler implementation, as the assbemler could easily recognize this and produce the correct code replacement for increment addressign mode. I guess the programmers just forgot this exception when coding the 'emulated instructions'.
The mspgcc assembler give the error 'addressing mode is not applicable for destination operand'. Here too, the assembler programmers missed the opportunity to implement the proper replacement. But at least you'll get an error message that will tell you what's going wrong (if you think a bit about what the instruciton really does)

s b said:

What exactly is the meaning/purpose of the "@" nomenclature, since it seems to only apply to source operands?  Is it equivalent to "0(Rx)", or is there some other power it has?

This is to common and universal that I can see how people might forget to mention it explicitly. Kind of like the stack growing downward in memory or 0-based array indexing. The fact the MSP430 works this way is quite obvious from the description of various operations.

So the first instruction would move the word after the instruction to R15, and advance the PC past that word. Execution would continue after the data word. Thus, the net effect would be that of an immediate operand.

The second would move the word after the instruction to R15, but not advance the PC, so execution would continue with the data word. The use of this operation is unclear, except in deliberately obscure code.

As for me, it all came from RTFM.

I don't see an IIRC anywhere in the doc I'm reading

I'm still ROTFLOL!

What exactly is the meaning/purpose of the "@" nomenclature, since it seems to only apply to source operands?  Is it equivalent to "0(Rx)", or is there some other power it has?

[/quote]

Ok, I think I see -- @R1 does not require the extra offset word, and only applies to the source operands because they ran out of addressing mode bits (only 1 bit for Ad field in the double operand instructions), otherwise they could have had an equivalent for the dest operand.  So it is a nomenclature that lets us tell the assembler the most efficient way to use a register as an address.

Thank you for these detailed discussions, they really help.

I am now slowly getting familiar with using the TI CCS assembler/compiler to program the MPS430G2231 and MPS430G2211 that came with the Launchpad (I'm mainly interested in the 2231 to begin with).

My first questions have to do with learning the rules involving the use of RAM, such as how the stack pointer (SP) is initialized, what variables are assigned to RAM and where, how would one store data in the Flash Memory if necessary.  The compiler and debugger hide a lot of stuff I'd like to see explicitly, so I need to get familiar with how to expose it and examine it.

I would also like to be able to use the system to load machine code directly into the MPS430 flash memory and/or RAM and start it running so I could try hand-assembling some code -- crazy I know but somehow makes it more real.

Regards,

-SB

s b said:

My first questions have to do with learning the rules involving the use of RAM, such as how the stack pointer (SP) is initialized, what variables are assigned to RAM and where,

I must admit that I once wrote my own reset function for the mspgcc (the original was disabling the WDT to avoid timeouts while copying the variables, which was inacceptable for my project)

If you program directly in assembly language, it's up to you to init the stack pointer: Just move its initial value into R1. That's all.

s b said:

how would one store data in the Flash Memory if necessary.

s b said:

I would also like to be able to use the system to load machine code directly into the MPS430 flash memory and/or RAM and start it running so I could try hand-assembling some code -- crazy I know but somehow makes it more real.

The elprotronic programming software is able to program a plain hex file to the MSP. (or MSPGCCs MSP430-JTAG, but it cannot handle the newer processors, a tleast not the version I have). You can produce your output in binary form and let it write to the MSP if you really want.

I guess I'm wondering -- where do you typically initialize the stack pointer in assembler -- to the highest address in RAM?  And in C (and assembler), how do you keep the stack from overwriting static variables, or simply running out of RAM?  Or at least have a clue how to manage RAM when there is so little of it and the stack is eating into it?  Seems like a lot of thought and planning might go into managing RAM.

It will take some time to look through the C library to see what is available, such as heap storage allocation, math functions, what are the speed and size considerations of the math functions, what precision arithmetic can be done reasonably efficiently, etc.

I'll be slowly looking at at these issues and will hopefully post some better-informed questions as time goes on.

Thanks for the guidance.

-SB

s b said:

where do you typically initialize the stack pointer in assembler -- to the highest address in RAM?

s b said:

And in C (and assembler), how do you keep the stack from overwriting static variables, or simply running out of RAM?

s b said:

what precision arithmetic can be done reasonably efficiently

Also, depending on the used compiler, the available implementations greatly differ. Much of the standard C library doesn't make much sense on an MSP (such as stdio, as there is no such thing liek a standard input or output). CCS, IAR and MSPGCC implement different subsets and to a different extent. Of course you can take any high-level source code for an STDLIB implementation and compile it for the MSP.

Thanks for the tips!  I'll have to look into Q-numbers.  Also probably should brush up on my "twos-complement" arithmetic, etc.

I'd like to do some A to D sampling and some digital low-pass or low band-pass filtering of the signal.  I think it will be very tight for time with an MSP430, so probably I'll need to use some tricks rather than straight math.  I'd like to sample at the maximum rate (200K p/s) but I'm pretty sure there wouldn't be enough computation time.  So I'll probably use some analog integration and sample around 15K p/s, but even then probably very tight for computation time.

Do you know anything about the "sample and hold" modes of the MSPG2231?  The family manual refers to "Sample-and-hold with programmable sample periods", and I'm wondering what that really means.

Regards,

-SB

s b said:

I'd like to sample at the maximum rate (200K p/s) but I'm pretty sure there wouldn't be enough computation time.

The ADC10/12 is an SA converter. It samples the input signal to a storage capacitor, then cuts off the connection to the input and does a successive approximation. It compares the stored value to Vref/2, then (based on teh result of this comparison) to Vref/4 or Vref/2+Vref/4 etc. MSB down to LSB. The hold time (tiime for the conversation itself) is n+1 clock cycles  (where n is the requested number of bits for ADC12A, for ADC10, it is fixed 13 clock cycles). But the preceding sampling time can be adjusted.

The input forms a low pass (sereis resistor and storage capacitor), so the longer you hold the input open, the more time the signal has to settle (for high-impedance sources) or to form an average (low-pass effect). With the ADC10SHTx bits in ADC10CTL0 can you define how many clock cycles this sampling period shall last.

Also, you can make your individual timing by directly controlling the input switch using a timer CCRx output or an external signal. Switch closed: sampling. Switch opened: begin converting (and 13 clock pulses later the result is provided). Gread for keeping the CPU in sleep mode and still gettign precisely timed conversion results.

Thanks for the good info.  I need to collect some of those numerical tricks.  I think I'll need 32 bit accumulators, if not 64 bit for my aps.

Sounds like I might be able to use the ACD10CTL0 to do some integration, need to know a little more about the series resistor and storage capacitor and how they are controlled.

The timer for the conversion sounds like it would be what I need for one version of the application I'm thinking of.

What about the idea of a "tracking" ADC, where the max and min levels of the ADC are adjusted to follow the waveform, in the hopes of faking more precision?

What kinds of applications do you use the MSP430 for?

Regards,

-SB

s b said:

What about the idea of a "tracking" ADC, where the max and min levels of the ADC are adjusted to follow the waveform, in the hopes of faking more precision?

To increase the results of the AD10/AD12, you can modulate a small (best: 1LSB worth), high-frequency signal to the input. Then you sample several times (at least over one complete cycle of this signal) and build an average. The signal will shift the input voltage 'over the edge' to the next higher bit, but only for some fractions of its wavelength. So the average of several amples during one wave gives you additional significant bits, even if the input signal is static and would otherwise give you always exactly the same value.

(sometimes, signal noise does the same for you, but then you don't know th eperiod and therefore the exact magnitude of its influence)

s b said:

What kinds of applications do you use the MSP430 for?

Those are some interesting projects you have worked on!  These microcontrollers have a lot of potential due to their low cost and low power.

Thanks for the ADC info - I suspect I will eventually wish I was using at least a 16 bit ADC, but I'll try whatever tricks I can with the 10 bit ADC.  You mentioned the "dithering" technique with the small extra signal.  There will be some natural noise in the system that may work in that regard.  Although I want to sample at at least 15K p/s, the extracted signal is quite low frequency, maybe 10 Hz, so the digital filter will be doing the "averaging". 

Now, the digital filter is another question.  I'd like to start with a really simple filter, like Y_t = .99 * Y_t-1+ .01 * X_t , but even that arithmetic may strain the processor.

I saw an impressive MSP430 filtering example in a paper called "

Wave Digital Filtering Using the MSP430" by Kripasagar Venkat -- way over my head at this time.

So I'll little-by-little try to get my feet wet with this microcontroller - it will go slow due to other priorities.

Regards,

-SB

s b said:

These microcontrollers have a lot of potential due to their low cost and low power.

s b said:

like Y_t = .99 * Y_t-1+ .01 * X_t , but even that arithmetic may strain the processor.

Ultra-low power is not a main issue for my application either, even though the application is battery-powered.  However, it makes me want to think of other ideas that might take advantage of such stingy power use.  Of course, most of the power savings are due to the low-duty modes, so that limits the aps somewhat.  Anyway, I hope this microcontroller is worth investing some time in -- I got sucked in by the Launchpad, which I think is a great way to market these devices.  If IBM had given OS/2 away free to college students, who knows what would be running on PCs today!

try Y_t= (1014*Y_t-1+X_t)>>10. (it's the same except a 0.2% error, and may be further refined)

Exactly the kind of useful tip I'm interested in.  Thanks!

-SB

s b said:

try Y_t= (1014*Y_t-1+X_t)>>10. (it's the same except a 0.2% error, and may be further refined)

[/quote]It's actually X_t*10 :)

The basic idea was to multiply the fractions by 1024 and the divide the result by 1024, which is a simple shift.
You can reduce the error by multiplying/shifting with 2048 or 4096, if the result of the idividual multiplication operations still fits into a long variable.

s b said:

Exactly the kind of useful tip I'm interested in

Sometimes precision isn't as important as speed. Many people tend to forget it. The same people who use FFT instead of the way more accurate but by magnitudes slower default Fourier Transformation. :)

One key rule for MSPs (and othe rmicrocontrollers) is: "If you can do it at compiletime, don't do it at runtime".  Another one is " keep things simple. And if they are not simple, make them simple"
It would fit well for normal PC programs too. But for microcontrollers, it is essential.