MSP430F6746: ACLK for WDT-A clock source

Koichiro Tashiro

Part Number: MSP430F6746

Hi,

I have a question from my customer.

Suppose ACLK source is XT1 LF (the default condition) and WDT-A is sourced from ACLK.
At device power-up, XT1 LF is not stabilized, so ACLK is automatically switched to REFOCLK, according to user's manual section 5.2.12 "UCS Module Fail-Safe Operation".

On the other hand, section 16.2.5 Clock Fail-Safe Feature in WDT-A says:

As ACLK is maintained thanks to the UCS fail-safe, I guess the fail-safe feature in WDT-A is not triggered at power-up.
So WDT-A is sourced from ACLK (REFOCLK) not VLOCLK.
Correct?

Thanks and regards,
Koichiro Tashiro

over 3 years ago

0 Dennis Lehman over 3 years ago

TI__Guru 71216 points

Hi Koichiro,

After a POR the default clock source for the WDTA is the SMCLK. After POR you can switch to ACLK or VLOCLK, usually for low power considerations. If you use ACLK, you can source it with XT1 or REFO. NOW, according to section 16.2.5 in the users guide, if SMCLK or ACLK fails, VLOCLK becomes the default clock.

Does this help?

0 Koichiro Tashiro over 3 years ago in reply to Dennis Lehman

TI__Mastermind 22945 points

Hi Dennis,

Dennis Lehman said:
NOW, according to section 16.2.5 in the users guide, if SMCLK or ACLK fails, VLOCLK becomes the default clock.

The above "ACLK fails" condition includes the case ACLK source is switched from XT1 to REFO by UCS fail-safe operation?

Thanks and regards,
Koichiro Tashiro