MSP430FR5043: BSL frequency issue

Hi Cherry,

How is the customer verifying that the main frequency is 8MHz after switching from 16MHz?

Hi Dennis,

Thanks for your help.

Dennis Lehman said:

How is the customer verifying that the main frequency is 8MHz after switching from 16MHz?

The customer verifies the frequency using the CS_getMCLK() function in the MSP430 library. A slight delay after modifying the frequency shows that the function returns 8000000.

They have been use this method to monitor the monolithic frequency before using MSP432, and it can work properly.

Also here's an additional question:

Tried with an external 16-MHz crystal, and the result is that if you use HFXT, the BSL will not succeed anyway, and the following conditions must be met for the BSL to succeed:

a. before BSL, switch to DCO and MCLK at 8 MHz.

b. The monolithic cannot use the HFXT at any time and sets the MCLK to 16 MHz (that is, it can initialize with HFXT and 8 MHz MCLK, and switch to DCO when BSL is needed).

The frequency at which the MCLK/SMCLK/ACLK is output directly from the monolithic pins is correct, and the BSL is entered by a software call in the program.

Thanks and regards,

Cherry

Hi Cherry,  when the customer is operating at 16MHz, they should be using 1 wait state.  Do they reset the wait state = 0 when dropping down to 8MHz?

Hi Dennis,

The system initialization is as follows:

CS_setDCOFreq(CS_DCORSEL_1,CS_DCOFSEL_4); //High range and 16MHz

 CS_initClockSignal(CS_MCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);
CS_initClockSignal(CS_SMCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_2);

FRCTL0 = (FRCTLPW | NWAITS_1);

…………………………………………………………………………

When BSL is required, after decreasing the frequency, the wait state has been reset to 0. But the issue still remains, and BSL still cannot be operate. The code is as follows:

CS_setDCOFreq(CS_DCORSEL_1,CS_DCOFSEL_3); //High range and 8MHz
CS_initClockSignal(CS_MCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);
CS_initClockSignal(CS_SMCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);
// Configure wait states to be able to use 8 MHz MCLK
FRCTL0 = (FRCTLPW | NWAITS_0);
__delay_cycles(16000);
__disable_interrupt(); // to eliminate echo of int8_ts
((void (*)())0x1000)(); // jump to Z-area of BSL

Thanks and regards,

Cherry

Hi,

May I know is there any update?

Thanks and regards,

Cherry

Hi Cherry,

I'm trying to duplicate this issue.

Hi Dennis,

Thanks and expect the updates.

Best Regards,

Cherry

Hi Cherry,

I cannot duplicate the problem.  It works for me using MSPFET programmer.  What tool is the customer using?

Hi Dennis,

Thanks for your working.

They also debug and download the code with the MSPFET programr and use a normal USB-to-serial cable to BSL through the UART3 port.

Is it required to switch from 16 MHz to 8 MHz for BSL only when using MSPFET? And the other cable can only be used at 8 MHz all the time?

Thanks and regards,

Cherry

Hi,

May I know is there any update? Thanks.

Best Regards,

Cherry

Hi Cherry,

Since I cannot duplicate the issue, can the customer try reducing the code size to the absolute minimum and see if the problem still occurs.  I have attached my project that works as an example.

#include <msp430.h> 
#include <stdbool.h>
#include <stdint.h>



/**
 * main.c
 */
int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;	// stop watchdog timer
	
	// GPIO initialization specific to HW
    P1DIR = (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7);
    P1OUT = 0x00;
    P1SEL0 = (BIT2 | BIT3);

    P2DIR  = (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT6 | BIT7);
    // enable pullup on P2
    P2OUT  = BIT5;
    P2REN  = BIT5;

    PM5CTL0 &= ~LOCKLPM5;

    // FIRST START UP AT 16MHZ
    // Configure one FRAM waitstate as required by the device datasheet for MCLK
    // operation beyond 8MHz _before_ configuring the clock system.
    FRCTL0 = FRCTLPW | NWAITS_1;

    // Clock System Setup
    CSCTL0_H = CSKEY_H;                     // Unlock CS registers
    CSCTL1 = DCOFSEL_0;                     // Set DCO to 1MHz
    // Set SMCLK = MCLK = DCO, ACLK = VLOCLK
    CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;
    // Per Device Errata set divider to 4 before changing frequency to
    // prevent out of spec operation from overshoot transient
    CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4;   // Set all corresponding clk sources to divide by 4 for errata
    CSCTL1 = DCOFSEL_4 | DCORSEL;           // Set DCO to 16MHz
    // Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
    __delay_cycles(60);
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;   // Set all dividers to 1 for 16MHz operation
    CSCTL0_H = 0;                           // Lock CS registers                      // Lock CS registers

    // THEN DROP DOWN TO 8MHZ BEFORE INVOKING BSL
    __delay_cycles(16000000);

    CSCTL0_H = CSKEY_H;                     // Unlock CS registers
    CSCTL1 = DCOFSEL_0;                     // Set DCO to 1MHz
    // Per Device Errata set divider to 4 before changing frequency to
    // prevent out of spec operation from overshoot transient
    CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4;   // Set all corresponding clk sources to divide by 4 for errata
    CSCTL1 = DCOFSEL_3 | DCORSEL;           // Set DCO to 8MHz
    // Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
    __delay_cycles(60);
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;   // Set all dividers to 1 for 16MHz operation
    CSCTL0_H = 0;                           // Lock CS registers                      // Lock CS registers

    // Configure zero FRAM waitstate as required by the device datasheet for MCLK

      FRCTL0 = FRCTLPW | NWAITS_0;


      while(1)
      {
          // Toggle LED1 to signal application is running
          P1OUT ^= BIT0;

          // If switch is pressed, enter BSL mode
          if((P2IN & BIT5) != BIT5)
          {
              // Set LED2 to signal entry into BSL
              P1OUT |= BIT1;
             ((void (*)())0x1000) ();
          }

          _delay_cycles(1000000);
      }

}

Hello Denis,

Thanks and it does work!

Could you help point to where can this errata be found? 

Thanks and regards,

Cherry

Hello Denis,

May I know is there any update regarding the question in my last response?

Thanks and regards,

Cherry