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MSP430F5358: Query on Multimaster I2C Mode

Anjali Karthik
Prodigy 50 points
Part Number: MSP430F5358


Hi,

We are having a query regarding multimaster mode in I2C communication. We are using MSP430F5358 in our project as a multimaster in one USCI I2C module (where the other multimaster is Rfsoc) and as a slave in another module. We have the following queries :

1. Is there any changes in the basic initialization configuration of I2C multi-master? If so, could you please provide some example codes regarding that. For single master, we have used the following code for the I2C master initialization :

/*
 * I2C INITIALIZATION
 */
void I2c_init()
{
    GPIO_setAsPeripheralModuleFunctionInputPin(
    GPIO_PORT_P3,
                                               GPIO_PIN0 + GPIO_PIN1);
    USCI_B_I2C_initMasterParam i2c_params_24FC256 = { 0 };
    i2c_params_24FC256.selectClockSource = USCI_B_I2C_CLOCKSOURCE_SMCLK;
    i2c_params_24FC256.i2cClk = UCS_getSMCLK();
    i2c_params_24FC256.dataRate = USCI_B_I2C_SET_DATA_RATE_400KBPS;

    /* Initializing I2C Master to SMCLK at 100khz with no autostop */
    USCI_B_I2C_initMaster(USCI_B0_BASE, &i2c_params_24FC256);
}

2. From the information we gathered online, we understood that we have to do an isI2cBusBusy check, before doing any I2C transaction to avoid conflicts. Is there any additional parameters to be considered?

It would be helpful if you could provide any information regarding this.

 

  • 0
    Guru 100355 points

    [Disclaimer: I have not actually used a multi-master bus, but I understand the principles. If someone
    contradicts me, believe that person.]


    1) Multi-master operation is described in the I2C Spec (UM10204 Rev 6) Section 3.1.8 and the F5 User Guide
    (SLAU208Q) Section 38.3.4.3 and Table 38-1.
    2) I don't know of any TI Examples for doing this.
    3) Your RFSoC/MSP430 direct link appears to be a separate bus (I2C_2), so it doesn't enter into this.
    4) In a multi-master bus, it is possible for one master to address the other as a slave. You didn't mention
    wanting to do this, but it would require some further steps.


    5) To use Multi-Master mode you need to set UCBxCTL0:UCMM=1. I don't see a driverlib function that does this
    (for the USCI), so you'll need a separate sequence something like:
    > UCB0CTL1 |= UCSWRST; // Into reset
    > UCB0CTL0 |= UCMM; // Multi-Master
    > UCB0CTL1 &= ~UCSWRST; // Out of reset
    6) You need to detect the UCALIFG ("Arbitration Lost") condition. [Ref UG Figs 38-12/13, down near the bottom]
    If you see this, the USCI has set UCMST=0 [Ref UG Table 38-1] and you need to reconfigure your master (set
    UCMST=1) before the next transaction.


    7) Check the Errata Sheet (SLAZ496AB). USCI34 looks significant, but there's a Workaround offered.
    8) Checking for bus-busy ahead of time doesn't hurt but doesn't really help either (race). The USCI does this
    work for you anyway.

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