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MSP-EXP430F5529LP: MSP430F5529LP: SPI clock Configuration

tr
Prodigy 220 points
Part Number: MSP-EXP430F5529LP
Other Parts Discussed in Thread: PGA460-Q1, MSP430F5529, PGA460

Hi, team

I would like to run SPI communication at just 8MHz using MSP430F5529LP.

Where should I write the register?

I tried to write these register.

UCB1CTL1 =  UCSSEL_2; // source USCI clock from SMCLK

UCB1BR0 = 0x03; // set initial speed to 25/3MHz

However, MSP430F5529LP run at 8.33MHz clock and didn't recognize the correct value.

(when UCB1BR0 = 0x04, it can communicate normally at 6.25MHz clock.)

regards,

  • 0
    Guru 99105 points

    The USCI has only a simple divider (BR0/1) from its source clock, so for a given SMCLK speed there are some SCK speeds you can't achieve. If you were to run SMCLK at 24MHz, you could get exactly 24/3=8MHz.

    Since SPI is synchronous, the exact speed it runs at (even a non-constant speed) rarely matters. What is your application?

  • 0 in reply to Bruce McKenney
    Prodigy 220 points

    Hi,

    I'm sorry for the late reply.

    > The USCI has only a simple divider (BR0/1) from its source clock, so for a given SMCLK speed there are some SCK speeds you can't achieve. If you were > to run SMCLK at 24MHz, you could get exactly 24/3=8MHz.

    Does it mean I need to attach external 24MHz clock?

    >Since SPI is synchronous, the exact speed it runs at (even a non-constant speed) rarely matters. What is your application?

    I would like to get a raw signal data from PGA460-Q1.
    For that, SPI clock is required at 8MHz.


    MSP430F5529LP                 PGA460-Q1
    ---------------------------             -------------
                                    | 　　　|
    P4.1(UCB1RXBUF)| -------> |RX
    P4.2(UCB1TXBUF)| <------- |TX
         P4.3(UCB1CLK)| ---------|SCLK
    　　　　　   　　　|            |

    When I run SPI at 8.333MHz clock, MSP430F5529 recognizes a wrong byte.

    For example,

    0x60(correct) → 0xC1(wrong)

    At 6.25MHz clock, MSP430F5529 recognize the correct byte 0x60.


    I checked P4.1 and P4.3 signal from PGA460 using an oscilloscope. PGA460-Q1 seems to send 0x60 even at 8.333MHz(I set CPOL=0, CPHA=1).


    Therefore, I think it's the problem with MSP430F5529.

    Thank you for your help.

  • 0 in reply to tr
    Guru 99105 points

    1) CPHA=1 (and CPOL=0) corresponds to UCCKPH=0 (and UCCKPL=0). Is that how you have it set? (CPHA=1 does match the description in PGA460-Q1  data sheet (SLASEC8B) Sec 7.3.6.2.1.8.)

    2) The data sheet  Sec 6.15 does say max SPI is 8Mbps, even though Sec 6.14 (tBIT_USART) seems to suggest it can go faster. Maybe this really is a hard limit.

    3) The DCO can run at 24MHz. Changing it will of course also change MCLK but maybe(?) a 4% reduction in your system speed won't be noticeable. TI Example MSP430F55xx_UCS_10.c sets the DCO to 25MHz, but changing its UCSCTL2 constant from 762 to (24MHz/32768Hz-1)=731 will set the FLL for 24MHz. (I expect you have similar code in your program.)

    https://dev.ti.com/tirex/explore/node?node=ADKytAZZqpKrkO1QRCzW1Q__IOGqZri__LATEST

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