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MSP430FR59941: Configure HFX lines

a b
Prodigy 190 points

Part Number: MSP430FR59941
Other Parts Discussed in Thread: MSP430FR5962, MSP430FR5964, MSP430FR5994, MSP430FR5992,

I am looking at this doc:

MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 202

Page 121

Table 9-37. Port PJ (PJ.6 and PJ.7) Pin Functions

For HFX operation, the table clearly shows PJSEL0.7 as don't care, and PJSEL1.6 as zero.

Then there is this footnote:

Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are
configured for crystal operation and PJSEL1.6 and PJSEL0.7 are do not care. When HFXTBYPASS = 1, PJ.6 is configured for bypass
operation and PJ.7 is configured as general-purpose I/O

Could someone suggest which is correct, the table or the footnote?

Thank you,

ML

  • 0
    TI__Guru 56685 points

    Hello ML,

    The footnote has a typo as it should match the table above. The highlighted section should be "PJSEL1.7 and PJSEL0.7".

    The state of the pin is dependent on the mode. It can be configured as GP I/O or for HFXT operation. While in HFXT mode, it can also be in HFXT Bypass mode. when in Bypass mode, there is no need for HFXTOUT as you are only inputting a digital clock signal. So this mode automatically configures J.7 to GP I/O, regardless of the SELx bit settings. 

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