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MSP430FR2355: Where can I find the number of clock cycles for each instruction

TICL
Prodigy 190 points
Part Number: MSP430FR2355

Coming from programming assembly in PIC I'm so used to looking up their instruction set summary table where I can readily check for the CPU cycles for different instructions (e.g. 1 cycles for ADDWF, 2 cycles for CALL etc.). Specifically for my application I need to know the exact cycles each instruction takes (x-cycles for decrement, y-cycles for branch, z-cycles for rotate  etc...), but now I'm weeks into MSP430 I'm still not able to locate these information in the TI's MSP430FR2x Family User Guide:  

They are NOT in 4.6 Instruction Set Description

They are NOT in 4.6.2 MSP Instructions Description

Only in 4.5.1.5.3 Jump Instructions Cycles and Lengths did I find JUMP takes 2 cycles .... but that's only for jump instructions through, but what about other instructions?  So I literally searched for each operand and yet no information found.

Appreciate if someone can tell me where they are or is there a separate document or table that lists out the number of cycles for each instruction operand.

  • 0
    Guru 34483 points

    You can find this in slau208 MSP430x5xx and MSP430x6xx Family User's Guide, in section 6.5.1.5 MSP430 Instruction Execution. Everything is there, but it is compressed, one example for more identical type of instructions.

    FRAM is with same CPUXv2 as 5xx/6xx flash family. However, while with MSP430x2xx number of CPU cycles is fixed and code timing calibrated on number of CPU cycle works without issues, there are some issue with CPUXv2, and especially with FRAM. There are undocumented staff, and you should test it by yourself to be sure if something that you want is possible. For example...

    forum.43oh.com/.../

  • 0
    Guru 24435 points

    As stated, it is all in the family guide. But as a first order approximation, it is one cycle per memory access.

  • 0 in reply to David Schultz
    Prodigy 190 points

    if 1 cycle per *.b access, approximating 2 cycles per *.w access should be fairly accurate I guess? 

  • 0 in reply to TICL
    Guru 34483 points

    No, it is not related to .b and .w

    For example,  mova R4, R5  will transfer 20-bit value from one register to another in one CPU cycle. CPUXv2 is with 20-bit registers.

  • 0
    Prodigy 235 points

    I have similar experience with this device. Finding this in slau208 more frustrating. Can not TEXAS find a better way of supporting its users ,without having to spend countless number of hours in sifting through number of pages..

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