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MSP430F6777A: MSP430F6777A measuring signal with or without pwm with ADC10 periph.

fhiz
Prodigy 110 points
Part Number: MSP430F6777A

Hi

There is a 1-kHz, ±12-V PWM signal, duty cycle 10%~53,3. This signal is scaled between 0 and 3.3 volts(for reading with adc).  Also this pwm is generated by mcu with timer. I need to keep measuring the signal with or without pwm constantly.

What is the best way to read adc value? I need to read voltage with adc both edges (rising and falling edge) When pwm signal is active I need to meausere both rising and falling edge. But sametime, I need to keep measuring signal without pwm.

(its control pilot signal for ev)

  • 0
    TI__Guru 71216 points

    Hi Fhiz,

    Not sure I understand completely here, but are you asking if you can use both rising and falling edges of the PWM to trigger an ADC reading?

  • 0 in reply to Dennis Lehman
    Prodigy 110 points

    Hi Dennis,

    Yes. I marked in the picture where I need to read

  • 0 in reply to fhiz
    TI__Guru 71216 points

    Thanks Fhiz for the clarification.

    fhiz said:
    There is a 1-kHz, ±12-V PWM signal, duty cycle 10%~53,3. This signal is scaled between 0 and 3.3 volts(for reading with adc). 

    Ok, then it looks like the minimum "on" time for the PWM @ 10% duty cycle would be 100usec. Rather than trying to perform the measurements just after the rising or falling edge, what if you just "oversampled" at a 50usec (20kHz) rate continuously?  The downside to this is it will consume a good portion of the CPU bandwidth.

    So, I'm thinking, to make less work for the CPU, the ADC10 has a window comparator mode that will generate a separate interrupt depending on if the measured value is above the ADC10HI or below the ADC10LO thresholds. 

    Here is an diagram showing what I'm describing.

    Here is a code example showing how the ADC window comparator interrupts can be handled.  I would then consider the following.  Since you really only care about taking one measurement after each transition, here is a scheme you can use to limit the number of CPU interrupts to only one per transition.  Full disclosure - this is just an idea and not something I have actually tried.  You may have to tweak a few things to get it working.

    Setup

    • Make sure you set appropriate HI and LO threshholds
    • Clear all interrupt flags and enable both ADC10HIIE and ADC10LOIE
    • I believe you would set the "repeat single channel mode" and set the ADC10MSC bit to perform continuous sampling

    Sampling and ISR handlers

    • Sample #1 - Voltage > ADC10HI threshold
      • ADC10HIIFG is now set to 1.
      • CPU vectors to ADC10 ISR and in the ADC10HI portion of the ISR do the following:
        • Clear ADC10HIIFG
        • Read the ADC result
        • Disable ADC10HIIE to prevent subsequent ADC10HI interrupts.
        • Enable ADC10LOIE
    • Sample #2 - Voltage > ADC10HI threshold
      • ADC10HIIE = 0 so, ADC10LOIFG and ADC10HIIFG = 0 and CPU not interrupted
    • Sample #3 - Voltage < ADC10LO threshold
      • ADC10LOIFG is now set to 1.
      • CPU vectors to ADC10 ISR and in the ADC10LO portion of the ISR do the following:
        • Clear ADC10LOIFG
        • Read ADC result
        • Disable ADC10LOIE to prevent subsequent ADC10LO interrupts
        • Enable ADC10HIIE
    • Sample #4 - Voltage < ADC10LO threshold
      • ADC10LOIE = 0 so, ADC10LOIFG and ADC10HIIFG = 0 and CPU not interrupted
    • Sample #5... - repeat sequence

    Hopefully this helps.  Let me know either way.

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