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MSP430F6636: 32.768KHz crystal selection

Ritul Patel1
Prodigy 70 points
Part Number: MSP430F6636


Hello,

We want to use an external 32.768KHz crystal for the MSP430F6636 controller at XIN & XOUT pins and have the below queries.

1. Existing crystal ABS07W-32.768KHZ-J-1-T and define integrated effective load cap. 5.5pf by using XTS=0 and XCAPx=1 in the MCU datasheet. So, No need to connect the external load cap. Is our understanding correct?

2. We want to define an alternate 32.768KHz crystal ABS06-32.768KHZ-T. If considered integrated effective load cap. 5.5pf by using XTS=0 and XCAPx=1. So, For XT1DRIVEx = 0, CL,eff ≤ 6 pF. (Pg. 29 MCU datasheet) then oscillation allowance (OA_LF) 210Kohm (Pg. 28 MCU datasheet).

Here crystal ESR value from the datasheet: 90Kohm. Safety factor = OA_LF/ESR = 2.33 (suitable qualification- SLAA322D) but drive level calculation value 2.87uW using below formula which is greater than 0.5uW crystal drive level . Should we add an external series resistor and the safety factor value looks OK?

Drive_level =(ESR*((Pi*Fmax*C_tot)^2)*(Vpp^2))/2

Regards,

Ritul

  • 0
    TI__Mastermind 28075 points

    Hi Ritul,

    Ritul Patel1 said:
    1. Existing crystal ABS07W-32.768KHZ-J-1-T and define integrated effective load cap. 5.5pf by using XTS=0 and XCAPx=1 in the MCU datasheet. So, No need to connect the external load cap. Is our understanding correct?

    The Datasheet for the ABS07W indicates that the load capacitance should be 3pF. Keep in mind that the XCAP selection is already effective load capacitance, so you would be exceeding the oscillators datasheet recommendation by using the 5.5pF setting. Your traces will also add some capacitance, typically on the order of single pF, that will be layout dependent.

    My recommendation here would be to clear the XCAP bit (i.e. the CL,eff would be the 2pF pin capacitance in series with the other 2pF pin capacitance, or 1pF total), and use two 4pf capacitors, to get you the additional 2pF you need. Alternatively you could not-populate these, and see if your board parasitics get you close enough to the nominal crystal value of 3pF. There is a good chance your trace capacitance will be more than enough, and with the extra pads you can still make adjustments if you change crystals or just want to tune.

    Ritul Patel1 said:
    2. We want to define an alternate 32.768KHz crystal ABS06-32.768KHZ-T. If considered integrated effective load cap. 5.5pf by using XTS=0 and XCAPx=1. So, For XT1DRIVEx = 0, CL,eff ≤ 6 pF. (Pg. 29 MCU datasheet) then oscillation allowance (OA_LF) 210Kohm (Pg. 28 MCU datasheet).

    Keep in mind that the OA value is going to be dependent on a number of factors, such as the specific crystal and board layout. Also I should point out that the effective load capacitance on the ABS06 appears to be around 12.5pF, so you do have more options for settings of the XCAPx value when using this crystal. 

    Ritul Patel1 said:
    Drive_level =(ESR*((Pi*Fmax*C_tot)^2)*(Vpp^2))/2

    What values are you using for Fmax and C_tot here? I just want to verify your calculation results since that drive level looks high to me for such a low frequency crystal. 

    Best Regards,
    Brandon Fisher

  • 0 in reply to Brandon Fisher94
    Prodigy 70 points

    Hi Brandon,

    Thanks for the reply.

    Earlier we verified the correct load by measuring ACLK at the P1.0 MCU pin by using different XCAPx register values (without any external load capacitor connected) For your information, attached register setting file. Finalize XCAP=1 value due to measured reading being very close to 5MHz. Do we need to connect an external capacitor?

    1. XCAP = 0 -> ACLK = 5.05MHz

    2. XCAP = 1 - > ACLK = 4.99732MHz

    3. XCAP = 2 - > ACLK = 4.99723MHz

    4. XCAP = 3 -> ACLK = 4.99643MHz


 

     

2. Please check the below values for used in this calculation.

    Fmax= 32,768.75MHz (considered XTAL tolerance 20PPM + 3 PPM Aging = total 23 PPM)

    C_tot =C_required + C_Stray/2 + C_probe
           =20pf + 5pf/2 + 1pf (assumed)
           = 23.5pF
    Where C_required= 2(C_load)-Cstray = 2(12.5pF)-5pf(assumed) = 20pf

    Drive_level =(ESR*((Pi*Fmax*C_tot)^2)*(Vpp^2))/2
    ESR= 90K
    Vpp= 3.3V

    Calculated Drive level = 2.87uW which is greater than 0.5uW XTAL drive level.

    
Regards,
    Ritul
  • 0 in reply to Ritul Patel1
    TI__Mastermind 28075 points

    Hi Ritul,

    Thank you for your patience. 

    Ritul Patel1 said:

    Hi Brandon,

    Thanks for the reply.

    Earlier we verified the correct load by measuring ACLK at the P1.0 MCU pin by using different XCAPx register values (without any external load capacitor connected) For your information, attached register setting file. Finalize XCAP=1 value due to measured reading being very close to 5MHz. Do we need to connect an external capacitor?

    1. XCAP = 0 -> ACLK = 5.05MHz

    2. XCAP = 1 - > ACLK = 4.99732MHz

    3. XCAP = 2 - > ACLK = 4.99723MHz

    4. XCAP = 3 -> ACLK = 4.99643MHz

    That is up to your application and the regularity of the crystal itself. In other words, just because this 1 sample of a selected crystal works very well with these settings does not mean that every sample of that same crystal will be optimal at these settings. 

    That said if you need 12.5pF Load for that oscillator, and you are using XCAP = 1,  then you've got somewhere between 8.5pf (5.5pF + 3pf stray capacitance) to 14.5pf (5.5pF + 9pf Stray capacitance) depending on your parasitics. Which is around the correct value, and it does seem like you are getting decent frequency results here. I would still suggest leaving pads for external caps if you can, incase you want to switch oscillators or add capacitance later. I should also point out that the value of ACLK doesn't tell the whole story here either, as the quality of your clock signal may degrade under certain settings as well.

    Ritul Patel1 said:
    2. Please check the below values for used in this calculation.

    Fmax= 32,768.75MHz (considered XTAL tolerance 20PPM + 3 PPM Aging = total 23 PPM)

    C_tot =C_required + C_Stray/2 + C_probe
    =20pf + 5pf/2 + 1pf (assumed)
    = 23.5pF
    Where C_required= 2(C_load)-Cstray = 2(12.5pF)-5pf(assumed) = 20pf

    Drive_level =(ESR*((Pi*Fmax*C_tot)^2)*(Vpp^2))/2
    ESR= 90K
    Vpp= 3.3V

    Calculated Drive level = 2.87uW which is greater than 0.5uW XTAL drive level.

    I believe the correct value for C_Tot should be your load capacitance (C_L, including parasitic values) plus the oscillator capacitance (C0), which would hopefully not be more than 1-2 pf.

    You are targeting a load capacitance of 12.5pF, so at best you would have something around 12.5pF + 1pF or 13.5pF for C_total. That's ignoring probe capacitance, but you could add a pF or so if you want to account for that. 

    That said, you still get around 0.95uW of drive level for those values. you could use a series resistor as you suggested to dampen, but the cost would be a reduction in your effective safety factor.

    If you instead find a crystal with a lower ESR, and similar or lower load capacitance requirements, it would reduce your drive level and improve your safety factor at the same time. 

    Best Regards,
    Brandon Fisher

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