• State Resolved
  • Locked Locked
  • Replies 16 replies
  • Subscribers 81 subscribers
  • Views 2904 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

FRAM Based MSP430 requirements

gabriellegarda
Expert 1050 points
Other Parts Discussed in Thread: MSP-TS430RHA40A, MSP-EXP430FR5739, MSP430F2274, MSP430F2616

Hi,

 

 

I just wanted to know, can I use the IAR and the FET430UIF with the new fram microcontrollers without any upgrade?

 

 

thanks,

 

 

Gabriel Legarda

  • 0
    TI__Intellectual 1345 points

    Gabriel,

    You do not need anything besides the latest update of IAR EW and the same FET.  You will need a different target board, the MSP-TS430RHA40A that you can buy at http://estore.ti.com.

    Thanks,

    Jacob

  • 0 in reply to jborgeson
    Expert 1050 points

    Hi to all,

    Just another question,

    One of the advantages of the FRAM it's to use it like a RAM memory...  it will be possible to work in the new MSP430FR with FRAM for data and program or it will be only for program? why there is SRAM in the MSP430FR?, is there a way to use only FRAM for all?,

    the datasheet it's not so clear... it uses for the RAM the SRAM by default,

    thanks,

  • 0 in reply to gabriellegarda
    Guru 17650 points

    Hi gabriellegarda,

    you can use FRAM for all! Program/data storage and data storage.

    Find some information here http://www.ti.com/ww/en/mcu/fram_ultra_low_power_embedded_memory/index.htm?DCMP=FRAM&HQS=Other+BA+fram-b

    In addition, have a look at the linker command file for the MSP-EXP430FR5739 example software; they use FRAM for all and RAM for nothing.

    Kind regards
    aBUGSworstnightmare

    P.S. Nothing/Nobody prevents you from using RAM! Use RAM for the data you can loose i.e. in event of a power down, ...

  • 0 in reply to Joerg Quinten
    Expert 1050 points

    Ok I'm looking foward to receive my card and to have the final datasheet and guide for the MSP430FR... I'll try to use FRAM for all..

     

    thanks

  • 0 in reply to gabriellegarda
    TI__Intellectual 1345 points

    Gabriel,

    You can use FRAM as program or data memory.  This is enabled because the memory is byte addressable, the very high write endurance, and the fast write/read speed.  There is SRAM on this device for a couple reasons:

    1) People are comfortable with it and it is easier to port existing applications over to FRAM

    2) The FRAM only operates at 8MHz access speed.  The SRAM provides a built-in 2-way 4 word cache for 64-bit access to FRAM if you want to run at higher speeds than 8MHz.  Notice the system clock runs at up to 24MHz. 

    You can find out a lot more about this cache and how to maximize write speed in this app note.

    Maximizing FRAM Write Speed with MSP430FR57xx.

    Thanks,

    Jacob

  • 0 in reply to jborgeson
    Guru 17650 points

    Hi Jacob,

    looks like your the fist one who lets 'his pants down' on the new FRAM devices!

    As far as I know, TI claims an access time of 50ns for the FRAM process (refer to http://www.ti.com/ww/en/mcu/fram_ultra_low_power_embedded_memory/index.htm?DCMP=FRAM&HQS=Other+BA+fram-b#3) . Now that your telling us that it will only operate at 8MHz access speed (write speed without wait states; also written in the app note you're referring) the 50ns time must be the access time for reading from FRAM. Can anybody pls provide some more details on this?

    Some other question: When I want to run on MCLK = 24MHz what is my instruction cycle time? Is it 1/24*10^6 = 41.67ns or something completely different (remember: there's a cache in SRAM)?
    Is there a comparison chart regarding the troughput of the new FRAM series (compared to standard MSP430 with Flash and SRAM)? Some kind of benchmarking would be of particular interrest too (same code; it takes x seconds on FR Series and y seconds on standard product at same MCLK; i.e. 16MHz when comparing with MSP430F2274 again).

    And, last but not least, how does the cache work and what happens i.e. when the program executes a jump or call instruction?

    Kind regards
    aBUGSworstnightmare

    P.S. By the way: where to find SLAA499 - Migrating From the MSP430F2xx Family to the MSP430FR57xx Family?

  • 0 in reply to Joerg Quinten
    Expert 1050 points

    HI  aBUGSworstnightmare,


    MSP430 processor doesn't comes with a pipe line so each instruction will depend in its content, so minimum 4 or 5 clocks to pass the datapath. so I will say maybe 166ns for the fastest assembler instruction at 24Mhz, for example with the MSP430F2616 at 16Mhz, the instruction in C to write in the buffer of a port (P1OUT = outdata; )  takes 1us so 1us=1/(16MHZ / 4(datapath)*4(3 or 4 instructions assembler and delays hardware),)

     

    In anothers words MSP430 will not exploit all the capabilities cause it's not designed to be the fastest and performant microcontroller, well I'm talking about the processing unit,  maybe the access to the memory goes faster..........................

    In ARM or Cortex like Stellaris series you will maybe have 1 instruction per clock so 41,67ns per instruction

    Gabriel Legarda

  • 0 in reply to gabriellegarda
    Expert 1050 points

    well quoting the info of TI they assure you 50ns acces time for MSP430:

     

    In addition to lower power performance, FRAM can also maintain unmatched data throughput. MSP430 with embedded FRAM is capable of 50ns access times, enabling speeds up to 1400 kB/s.

    With FRAM, embedded memory is no longer the bottle neck of your application.

    FRAM can write more than 100x faster than flash, while consuming less power!

    • Test case
      • CPU speed @ 8MHz
      • Both memory options writing 512B memory blocks
    • FRAM max throughput = 1400kB/s @ 730μA
    • Flash max throughput = 12kB/s @ 2200μA

    Well access doesn't mean ready to use!

    regards

  • 0 in reply to Joerg Quinten
    TI__Intellectual 1345 points

    ABWN,

    I guess you could say that, but I prefer to be the one who "shows what's behind the curtain". 

    This is all information you could find out from the app note I linked to anyways.  FRAM itself is capable of 50ns switching time in the dipolar crystal.  Our memory structure and clocking system is set at 8MHz accesses of 64bit wide data.  This is another reason that the cache is useful, and also why the previously linked app note was written.

    The read time is the same as the write time because FRAM, like DRAM, requires a refresh when read. 

    If you run MCLK at 24MHz, then you have SRAM access times of 41.67ns.  There is a throughput chart in that app note that I linked in my last post.

    The cache function is outlined in section 5 of slau272, the FR57xx Family User's Guide.

    That app note you reference should be out by the end of this week.

    Thanks,

    Jacob

  • 0 in reply to gabriellegarda
    TI__Intellectual 1345 points

    Guys,

     

    That 1400KB/s number is real, and it's actually a conservative estimate.  If you use your MSP-EXP430FR5739 board and the GUI that comes with it in mode 1, you can see it go over 2MB/s write speeds.  This is through the cache and the features I discussed.

    2MB/s equals roughly 16 megabit direct memory bit by bit throughput off the 24MHz clock signal.  FRAM is fast. 

    regards

  • 0 in reply to jborgeson
    Guru 17650 points

    jborgeson said:

    ABWN,

    I guess you could say that, but I prefer to be the one who "shows what's behind the curtain". 

    Jacob, I fully agree! That's the phrase I couldn't remember when writing my post; so, I ended up with another one ;-)

    aBUGSworstnightmare

  • 0 in reply to gabriellegarda
    Guru 17650 points

    gabriellegarda said:

    HI  aBUGSworstnightmare,


    MSP430 processor doesn't comes with a pipe line so each instruction will depend in its content, so minimum 4 or 5 clocks to pass the datapath. so I will say maybe 166ns for the fastest assembler instruction at 24Mhz, for example with the MSP430F2616 at 16Mhz, the instruction in C to write in the buffer of a port (P1OUT = outdata; )  takes 1us so 1us=1/(16MHZ / 4(datapath)*4(3 or 4 instructions assembler and delays hardware),)

     

    In anothers words MSP430 will not exploit all the capabilities cause it's not designed to be the fastest and performant microcontroller, well I'm talking about the processing unit,  maybe the access to the memory goes faster..........................

    In ARM or Cortex like Stellaris series you will maybe have 1 instruction per clock so 41,67ns per instruction

    Hi Gabriel,

    yes, your right! MSP430 is not a RISC MCU (like i.e. Atmel AVR were most of the instructions are single cycle instructions) since it is designed for low power application. But you can have a low power application which needs some processing performance too, so you need to know the differences between of the ne FRAM series.

    Maybe the new application note (SLAA499) will have some more details.

    Rgds
    aBUGSworstnightmare

    P.S. Jacob, will the link in SLAA498.pdf work when the new app note is on available on TI's website? If not, it would be a good idea to update SLAA498 too. 

  • 0 in reply to Joerg Quinten
    TI__Intellectual 1345 points

    ABWN,

    The link to 498 should work.

     

    http://focus.ti.com/mcu/docs/litabsmultiplefilelist.tsp?sectionId=96&tabId=1502&literatureNumber=slaa498&docCategoryId=1&familyId=1751

     

    I just downloaded it.

    Thanks,

    Jacob

  • 0 in reply to jborgeson
    Guru 17650 points

    Hi Jacob,

    yes SLAA498 is not problem! I was talking about the link on page 1 of SLAA498, refering to SLAA499.

    Rgds
    aBUGSworstnightmare 

  • 0 in reply to Joerg Quinten
    Guru 227245 points

    aBUGSworstnightmare said:
    yes, your right! MSP430 is not a RISC MCU

    However, pipelining is just a possible implementation of RISC and not a reuirement. And the MSP does have a pilpeline. If the target of teh current instruction is a register, it can fetch the next instruction while doing the math and writing the result.
    It is important to know this, as it affects things like setting breakpoints after entering LPM (a breakpoint on the instruction after entering the LPM is triggered before LPM is entered, as the instruction is fetched at the same time the LPM enter instruction is executed) or clearing GIE (there still might be an interrupt after the next instruction after clearing GIE)

    RISC means 'Reduced Instruction Set' in the meaning of a set of reduced instructions. So no specific instructions for this and than, just generic ones. The MSP very well fulfils this requirement. (no POP wehen a MOV does the same, no EINT, when a BIS on the status register does the same etc.)
    The characteristics usually thoght to be a requirement for being RISC are just implementation details form the first implementations of a RISC machine. Not even teh requirement of a single cycle per instruction is originally RISC. Only keeping the instruction execution simple and short. Of course, a single cycle IS short, and a single (32 bit) word per instruction to allow a single read cycle IS fast. Howeve,r it takes 32 bits per instruction, even if 16 bits were sufficient. And the MSP instructions for moving an immediate value into a register (including call instructions) are 32 bit too if you just join the instruction with the data (as it is done on a Sparc RISC processor).
    However, this 'traditional' RISC model fails when you
    - have a von-Neumann machine and data writes or reads do require sequential read/write cycles as they access the same data bus as the code (the Atmels are Harvard-machines with separate code and data address and data busses)
    - do not have a hardware stack, so an ISR call needs to save a return address and the status.

    And if you want to access 16 or 8 bit data, you'll need a lot of instructions to handle this or waste a lot of memory by always using long int for everything. workign on an incoming data string on a Sparc is a big,bloated nightmare and actually slower than on any other processor (in cycles).

    On the bottom line, the MSP is more risc than most processors I've ever seen, while being way more resource-saving and programmer friendly than the machines that follow the commonly as 'RISC' accepted model.

    aBUGSworstnightmare said:
    so minimum 4 or 5 clocks to pass the datapath

    No, to add two registers and store the result, it just takes 1 cycle. Just like a Sparc processor. And a typical RISC simply does not have instructions to do any math with a memory source or target at all, so you'll need 4 instructions to read two values into two registers (clobbering the registers), add them and store them back. The MSP takes 4 to 5 cycles too, to add one memory content to another memory content, but doesn't clobber any register for this and requires only 6 instead of 16 bytes memory for the code.
    Moreover, you don't have 'delay slots' after every branch or call or jump, which too often need to be filled with a wasted 'NOP' as you cannot put anything useful there. Sure, one cycle per instruction intheory, but if you need to add a NOP after cetain instructions, that's two cycles in the field :)
    I onc programmed a Sparc in assembly. I don't want to write a C compiler for it - mostthings that are normal in C (inlcuding functton pointers) are big and bloated, if possible at all on a Sparc (you cannot call a function indirectly, as the call instruction in code memory contains the destination address hardcoded, so yuo'll have to simulate it somehow).

    The MSP is as RISC as anybody would like to go. More RISC would be less. :)

  • 0 in reply to Jens-Michael Gross
    Expert 1050 points

    Thanks Jean-Michael,

     

    I learned a lot, I'm not an MSP430 expert, I will like to become one, I know more about stellaris... I've read about MSP430 CPU and its quite interesting, 3 stage Pipeline and RISC processor, it doesn't seem so bad as I tough,

     

    Gabriel Legarda

**Attention** This is a public forum