MSP430I2040: Input circuit for SD24 (noise reduction)

Hi,

user1082833 said:

Firstly the constant signal shows a very hight  variation on the SD24MEMx word (noise). Only the hight byte is a stable byte, the medium byte has a noise of approximately 20 to 50 AD steps, and the lower byte is very aleatory (not usable). The comparison with an other hight impedance 16 bit AD-IC didn't shows theses problems (no significant noise on the lowest bit). What input filter circuit should we place just before the SD24 input, to decrease the input signal noise, and so to stabilise at least the 16 upper bits of the SD24MEMx result.

What is your Oversampling Rate (SD24OSR) set to when you are noticing the noise, and how high impedance is the signal you are connecting your ADC input to?

Are you using an internal or external reference?  Also, are you seeing this noise on all channels? 

user1082833 said:

Secondly, with the 2kHz signal, we don't know how to parameter the SD24 input and the SD24 register, because actually it seems, that we receive a sort of averaged result, witch is obviously false. Has someone a code example for a similar problem? Do we also need an input filter at the input of the SD24. What is the minimal conversion time from the conversion start to the ready result?

With your OSR set to 256 (default), you should be getting about a 4Khz output data rate, which for your 2kHz frequency would be right at the Nyquist frequency. Typically reducing the OSR would increase noise, but in your case if you are getting any aliasing it could show an improvement. For reference, the Modulation frequency for the MSP430I2040 is fixed at 1.024MHz, and with your known OSR value you can calculate your actual sample rate. The idea of a minimum sample time doesn't really apply here since the actual sampling frequency for this device is fixed.

You can take a look at section 5.1.3 of our Answers to Common Sigma-Delta ADC Questions on MSP MCUs guide to see an example of an N=2 RC anti-aliasing filter that you might implement here. As recommended there, an RC filter 100x below the modulation frequency should be sufficient for most Sigma Deltas. 

Best Regards,
Brandon Fisher

Thank you for your answer.

What is your Oversampling Rate (SD24OSR) set to when you are noticing the noise, and how high impedance is the signal you are connecting your ADC input to?

We use the default value for SD24OSR (OSR = 256). As shown in the "MSP430i2xx Family User's Guide (Rev. A)" page 350 (3.2.7.2 Digital Filter Output), I think that we must use this value if we want read the two upper bytes. Is that right, or should we use an other value?

The second ADC-IC, which didn't shows the noise on the answer word, has an input impedance of several MOhm. On the other hand, according to the datasheet, the MSP430i2040 has an input impedance of as less than 200KOhm for each input. Might this be a reason for the noise in the signal, because our output signal (wheatstone bridge) has an overall impedance of approximately 3KOhm between Vcc and Vss?

Are you using an internal or external reference?  Also, are you seeing this noise on all channels? 

Yes we are using the internal reference of 1,2V. The noise seems to be on all channels.

For reference, the Modulation frequency for the MSP430I2040 is fixed at 1.024MHz, and with your known OSR value you can calculate your actual sample rate. The idea of a minimum sample time doesn't really apply here since the actual sampling frequency for this device is fixed.

I couldn't find the calculation formula for the sample rate in the datasheet. Where is it written? Actually the sampling code for the 2KHz signal don't seems to work properly.

   //Initialisation:
   SD24CTL = SD24REFS;
   SD24CCTL0 = SD24SNGL | SD24DF;
   SD24INCTL0 = SD24GAIN_16;
   __delay_cycles(3200);
   ...
   //Start measure with the beginning of the lower edge of the 2KHz signal
   SD24CCTL0 |= SD24SC;
   ...
   //Read result (later)
   x = SD24MEM0;

What changes do you suggest in this code to obtain the real value of the lower edge signal? Actually it is a sort of random value between the lower and upper edge

You say that the result is unstable. Did you wait for the digital filter to settle? You can't just start up a Sigma-Delta ADC and expect perfect results immediately.

user1082833 said:

We use the default value for SD24OSR (OSR = 256). As shown in the "MSP430i2xx Family User's Guide (Rev. A)" page 350 (3.2.7.2 Digital Filter Output), I think that we must use this value if we want read the two upper bytes. Is that right, or should we use an other value?

No that is correct, you would need OSR set to 256 to get the upper bytes. I would take a look at adding the recommended anti-aliasing filter if you have nothing currently. 10kHz is the cutoff frequency that the Family User's Guide recommends. 

user1082833 said:

The second ADC-IC, which didn't shows the noise on the answer word, has an input impedance of several MOhm. On the other hand, according to the datasheet, the MSP430i2040 has an input impedance of as less than 200KOhm for each input. Might this be a reason for the noise in the signal, because our output signal (wheatstone bridge) has an overall impedance of approximately 3KOhm between Vcc and Vss?

A 3kOhm source impedance doesn't seem high enough to be the cause to me. Since the SD24 on this part doesn't have an integrated buffer, input impedance can be a concern, but your Wheatstone bridge impedance is pretty low. Is there any thing else here that may be adding to your impedance or coupled noise, perhaps a long cable? 

user1082833 said:

I couldn't find the calculation formula for the sample rate in the datasheet. Where is it written? Actually the sampling code for the 2KHz signal don't seems to work properly.

Section 5.2.1 of that Sigma Delta FAQ document I linked to in my prior post provides an explanation of how to get your sampling rate. 

As shown in that equation, the ADC Sampling frequency (F_S) is the frequency of modulation (F_M) over your oversampling rate (OSR). You may also hear sampling frequency sometimes referred to as your output data frequency, and in that case your modulation frequency may be called the sampling frequency. The language I've seen is not always consistent. What is important to understand is that on the Sigma Delta has a frequency which it outputs data at (in this case, 1.024 MHz/256 = 4kHz), and a frequency it is actually running at (1.024MHz). Those two are related by your Oversampling Rate. 

user1082833 said:

   //Initialisation:
   SD24CTL = SD24REFS;
   SD24CCTL0 = SD24SNGL | SD24DF;
   SD24INCTL0 = SD24GAIN_16;
   __delay_cycles(3200);

This portion of code looks fine to me. 

user1082833 said:

   //Start measure with the beginning of the lower edge of the 2KHz signal
   SD24CCTL0 |= SD24SC;

Here, how are you timing the lower edge of this signal and triggering the conversion? Is this happening inside an ISR?

user1082833 said:

   //Read result (later)
   x = SD24MEM0;

This portion also looks fine. Most of your code  in fact matches very closely with our examples. 

You could also try adding additional delay as David has suggested. That kind of a test should be fairly quick.

Best Regards,
Brandon Fisher

Thank you for your answer.

Yes I wait for the digital filter to settle. Furthermore, in this step of the development, the PCB is always powered on (Later, we must optimise with the LPM, power down, ..., but these problems aren't for now). Actually the first measure takes place several seconds after powering on (manual mode for testing).

There are no long cable on the analog side of the circuit. The length on the PCB between the wheatstone bridge and the MSP430 is around 5cm. Do we need extra capacitors to filter the noise.

Hardware:

As the measured bridge voltage is over the internal reference of 1.158V, we have inserted two additional resistors in serie with the internal 200K of the MSP430 so that Vin+ and Vin- are both at around 0.6V in the neutral position of the bridge. The capacitors have yet both 100nF.

Are there further recommendation for this circuit? Actually I don't understand exactly the internal working of the SD24. Do we need the two resistors to diminue the voltage at Vin+ and Vin- under the reference voltage, or could we directly connect the bridge to Vin+ and Vin-?

For SD24GAIN_16 the datasheet shows a value of Vref/GAIN=58mV. Does this mean that Vin+ and Vin- must both be under 0.58mV, or only that the difference (Vin+ - Vin-) must be under 0.58mV. Because if the first case is true, then we need absolutely a Rail-to-Rail Out Instrumentation Amplifier (INA333, ...) with Vin- set  to GND to fullfill these specifications. In the second case, I think that we could directly connect the bridge to the MSP430.

Software:

For the final version, we need to know exactly when the SD24MEMx value is ready. So I tried to use the following initialisation:
SD24CCTL0 = SD24SNGL | SD24DF | SD24OSR_256 | SD24IE;

And the associated reading function:
SD24CCTL0 |= SD24SC;
while (! ((SD24CCTL0 & SD24IFG))) {;}   //Waiting for the Interrupt
x = SD24MEM0;
SD24CCTL0 &= ~SD24IFG;

It seems to me that the SD24IFG flag isn't set at any time. It stacks in the while loop. Where is the error in the code?

You both enable the SD24 interrupt and pole the interrupt flag. One or the other will work but not both. If you enabled global interrupts then you had better have an interrupt service routine for this interrupt. (Hint: the IFG flag is automatically reset when you read the SD24MEM register.)

Even if the input was as you diagrammed it, those input impedances are not exactly 1% resistors. Not even 10%. So useless for accurately scaling your input voltages.

I don't see where you are waiting for the digital filter to settle. Setting SD24INTDLY for example.