MSP-EXP430FR5994: uart receive dma value wrap around

I have the BQ uart setup to receive with DMA trigger. 

I have dma_value set as uint16_t because measurement data size is uint16_t. However Initialization data is uint8_t. 

BQInitTest shows the correct sequence of initialization bytes.

But what I am seeing in dma_value is shown in picture dmaValue. I don't understand the byte ordering in dmaValue. BQ response to initalization is correct, as seen in the logic analyzer. I have attached the code for DMA setup and DMA ISR, uartSend. uartReceive is also attached, however the problem occurs before this.

extern uint16_t bq79600Addr;

extern BYTE autoaddr_response_frame[(1+6)*TOTALBOARDS];
extern uint16_t response_frame[(8)*TOTALBOARDS];

uint8_t uartRxLen;
uint16_t dma_value[(8)*TOTALBOARDS] = {0};
uint8_t startMeasure = 0;
uint8_t bqAddr = 0;

void DMA_Init(){
    __data20_write_long((uintptr_t)&BQUART_DMASA, (uintptr_t)&BQUART_RXBUF);
    __data20_write_long((uintptr_t)&BQUART_DMADA, (uintptr_t) dma_value);

    BQUART_DMACTL &= ~DMAEN;
    DMACTL0 |= BQUART_DMA_RX_TRIGGER;
    DMACTL4 |= DMARMWDIS;

    //Repeated single transfer; increment destination address; source address unchanged;
    //byte to byte transfer source to DMA; byte to byte transfer destination to DMA;
    //rising edge DMA trigger; DMA enable

    BQUART_DMACTL |= DMADT_4|DMADSTINCR_3|DMASRCINCR_0|DMASRCBYTE__BYTE|DMADSTBYTE__BYTE|DMA_TRIGGER_RISINGEDGE|DMAEN;

}


int ReadFrameReq(BYTE bID, uint16_t wAddr, BYTE bByteToReturn, BYTE bWriteType, BYTE rxLen) {
    bReturn = bByteToReturn - 1;

    uartRxLen = rxLen;

    //PN setting a flag to identify when BQ79600 address is being read
    if (wAddr == 0x2001)
        bqAddr = 1;
    if (wAddr != 0x2001)
        bqAddr = 0;

    if (bReturn > 127)
        return 0;

    return WriteFrame(bID, wAddr, &bReturn, 1, bWriteType);
}

void uartSend(int length, uint8_t * data){
    uint8_t i;

    BQUART_DMASZ = uartRxLen;
    BQUART_DMACTL |= DMAEN;
    BQUART_DMACTL |= DMAIE;


    for (i = 0; i < length; i++){
        while (!(BQUART_IFG & UCTXIFG));
        BQUART_TXBUF = data[i];
    }


}

void uartReceive(void){
uint8_t i;
uint8_t aaResp[7*TOTALBOARDS];

    if (startMeasure == 1){
        memcpy(response_frame, dma_value, uartRxLen);
    }

    if (bqAddr == 1){
        for (i = 0; i < 4; i++){
           aaResp[2*i] = (uint8_t) dma_value[i] & 0x00ff;
           aaResp[2*i+1] = (uint8_t) ((dma_value[i] & 0xff00) >> 8);

        }

        memcpy(autoaddr_response_frame, aaResp, uartRxLen+1);
        bq79600Addr = autoaddr_response_frame[4];
        startMeasure = 1;
    }


}

#pragma vector=DMA_VECTOR
__interrupt void dmaIsrHandler(void)
{
    switch(__even_in_range(DMAIV,  BQUART_DMAIV_IFG))
    {
    case BQUART_DMAIV_IFG:
        BQUART_DMACTL &= ~DMAIE;

        uartReceive();

        // Exit low power mode on wake-up
        __bic_SR_register_on_exit(LPM4_bits);
        break;
    case DMAIV_DMA0IFG:
        break;

    case DMAIV_DMA2IFG:
        break;

    case DMAIV_DMA3IFG:
            break;

    case DMAIV_DMA4IFG:
        break;

    case DMAIV_DMA5IFG:
        break;

    default: break;
    }
}