MSP430FG6626: MSP430: MSP430FG6626: SN75176A

Hiii this is Amol Gholap,

i have a question related RS485 communication.here i used the SN75176A IC for communication.i was tried transmitting as well receiving a data from microcontroller through interrupt base, here i observed no issue come during transmitting dada at buad rate 9600. but during the receiving time code was stuck inside the "  __bis_SR_register(LPM3_bits + GIE);       // General interrupts enabled  and entering low power mode 3 "

this line in my code. give me the proper solution to receive data to the microcontroller.also i will share the my code for reference below.

Highlighted in green color line having stuck issue!.

Source Code:

//******************************************************************************
// MSP430FG662x Demo - eUSCI_A0, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz ACLK
//
// Description: Echo a received character, RX ISR used. Normal mode is LPM3,
// eUSCI_A0 RX interrupt triggers TX Echo.
// ACLK = 32768Hz crystal, MCLK = SMCLK = DCO ~1.045MHz
// Baud rate divider with 32768Hz XTAL @9600 = 32768Hz/9600 = 3.41
// See User Guide for baud rate divider table
//
// Note that UCA0RXD and UCA0TXD need to be assigned pins via the PMAP
// controller.
//
// MSP430FG662x
// -----------------
// /|\ | XIN|-
// | | | 32kHz
// ---|RST XOUT|-
// | |
// | P2.0/UCA0TXD|------------>
// | | 9600 - 8N1
// | P2.1/UCA0RXD|<------------
//
// M. Swanson
// Texas Instruments Inc.
// April 2014
// Built with Code Composer Studio v5.5
//******************************************************************************
#include <msp430.h>

int ReceiveData;
int main(void)
{

WDTCTL = WDTPW | WDTHOLD; // Stop WDT
CTSD16CCTL0 |= CTSD16SC; // Workaround for CTSD16OFFG errata
do
{
CTSD16CTL &= ~CTSD16OFFG;
}
while (CTSD16CTL&CTSD16OFFG); // End of CTSD16OFFG workaround

while(BAKCTL & LOCKBAK) // Unlock XT1 pins for operation
BAKCTL &= ~(LOCKBAK);
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap


// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag

__enable_interrupt(); // enable all interrupts
__bis_SR_register(LPM3_bits + GIE); // General interrupts enabled // (LPM3_bits +)
__no_operation(); // For debugger


//----------------------------------------- Configuring MAX485 Control Lines ---------------------------------------//

P8SEL |= BIT4; // COMMON P8.4 to ~RE DE and...at P8.4
P8DIR |= BIT4; // common P8.4 -> DE,-> ~RE output P8.4
// P8OUT &= ~(BIT4); // ~RE & DE SET TO ZERO IN RECEIVING MODE

P8SEL |= 0x0C; // Assign P8.2 to UCA0TXD and...
P8DIR |= 0x0C; // P8.3 to UCA0RXD

UCA1CTL1 |= UCSWRST; // **Put state machine in reset**
UCA1CTL1 |= UCSSEL_1; // CLK = ACLK
UCA1BR0 = 0x03; // 32kHz/9600=3.41 (see User's Guide)
UCA1BR1 = 0x00; //
UCA1MCTL = UCBRS_3|UCBRF_0; // Modulation UCBRSx=3, UCBRFx=0
UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA1IE |= UCRXIE; // Enable USCI_A1 RX interrupt
//-----------------------------------******************************--------------------------------------------------------//


/*************************************************************************************************/

while(1)
{
// while (!(UCA1IFG&UCTXIFG)); // USCI_A1 TX buffer ready?
// UCA1TXBUF = 0xAA;
// __delay_cycles (48000);

}
}


/************************************RS485 ISR SETUP***************************/

// Echo back RXed character, confirm TX buffer is ready first//
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A1_VECTOR

__interrupt void USCI_A1_ISR(void)

#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A1_VECTOR))) USCI_A1_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCA1IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
P8OUT &= (~BIT4); // ~RE & DE SET TO ZERO IN RECEIVING MODE
while (!(UCA1IFG&UCTXIFG)); // USCI_A1 TX buffer ready?
ReceiveData=UCA1RXBUF;
P8SEL |= BIT4;
__delay_cycles (4800);
UCA1TXBUF = ReceiveData; // TX -> RXed character
__delay_cycles (4800);
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
/*****************************************************************************************************************************/