MSP430F6736A: Increment in amplitude

What do you mean with amplitude of the acquired sample. What is the problem with the get wave?

As I know the ADC clock should not be so high.

Hi Eason,

Eason Zhou said:

What do you mean with amplitude of the acquired sample. What is the problem with the get wave?

The they meant by that is the voltage value after using the conversion formula,
Voltage=Sample*Reference voltage/Full scale value.
Ref voltage is taken as 1.2 V and
Full scale value as 224755712(Calculated for OSR=607)

When SMCLK is 24MHz(23*1024*1024), SD24DIVx in SD24BCTL0 Register is set as 22 so that modulator clock frequency, fM=1.1MHz

The problem with the acquired signal is that, for the same input ,ADC output increases with time.
For a 200mV peak-to-peak sine signal, the below observations are made,

Time of observation Minimum ADC O/P Maximum ADC O/P Peak-to-peak (Max-Min)
At Initial t = 0 -18285950 18854464 18854464
After 20min -19823072 20038638 20038638


When SMCLK is 1.1MHz no such increment is observed.

I hope this helps.

Regards,

Marvin

It is quite strange.

Can customer double check about the clock frequency by output it?

Hi Eason,

The customer initially set SMCLK and MCLK as 1.1MHz. This clock was not enough for their computation and tried to increase MCLK to 16MHz by changing the DCO frequency. MCLK and SMCLK are sourced by DCOCLKDIV (default configuration). MCLK and SMCLK became 16MHz.

Since SD24 modulation frequency cannot be that high, the customer set SD24 modulation frequency 1.1MHz by configuring the SD24DIVx field in SD24B control register 0. Then they observed the abnormality mentioned in this thread.

Currently, they changed SMCLK to 1.1MHz (MCLK=16MHz) by setting the DIVS field in the UCSCTL5 register without configuring the SD24DIVx field in the SD24B control register. In this configuration, they have not observed any such increments(from constant input from the function generator).
The above configuration (SMCLK = 1.1MHz and MCLK=16MHz) is used as a temporary solution for the problem.

Also, the customer checked pin 53 but observed no clock in the line. Is there a pin configuration to observe the clock?.

Is this the correct solution to this? or is there any better solution?

I hope this helps.

Regards,

Marvin

Hi Marvin,

Sorry to be late.

Customer need to set the P2SEL then they can output the SDCLK.

I think the solution is acceptable. 

Eason