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MSP430F5437A: Consequences of frequent changes to the MCLK speed.

RD
Intellectual 280 points
Part Number: MSP430F5437A


Debugging some issues on an existing product.

General Question:
MCLK is set to 4MHz, but the firmware changes it to 8MHz every 16ms, while performing some ADC calculations, and then switches back to 4MHz.
(Assuming it was implemented as some power saving feature)
DVCC is 3.3V, PMMCOREV is always 0.

Are there any adverse consequences of changing the MCLK speed this often?

Thank you.

  • 0
    TI__Guru 56685 points

    Hello RD,

    No real downsides. you may have some "deadtime" for a clock cycle or two when switching. Are you trying to get through some math calculations faster, or trying to hit a certain ADC sample frequency? For you could use MODOSC as your aDC clock source so you don't have to switch MCLK. Or you could have MCLK set at 4MHz while having SMCLK at 8MHz and modulate when SMLCK is active. Here the ADC would run off of SMCLK. 

    One other point to make is since you are trying to bump up to 8 MHz, I would recommend setting the device up to VCORE Level 1. Its a hard limit at 8MHz, so any overshoot can be trouble, which can happen when switching frequency or temp drift. 

  • 0 in reply to Jace H
    Intellectual 280 points

    Thank you Jace.  Understood.
    Just to clarify, is there a reason you recommended moving up to VCORE Level 2, and not set it to Level 1?  (we are currently at 0).
    We have a very power conscious application and would like to do everything possible to save on power consumption. 

  • 0 in reply to RD
    TI__Guru 56685 points

    RD,

    I skipped a level here sorry about that. (Was thinking 2nd power level which is level 1). VORE Level 1 will be fine. I'll edit my original post to avoid future confusion. 

    The best thing you can do is to stay in an LPM for as long as possible. It could actually be lower average power to operate at a higher frequency for a shorter period of time, then go to as deep a sleep as you can. It depends on your application and if it can handle bursty current and delayed reaction from deeper sleep modes. 

  • 0 in reply to Jace H
    Intellectual 280 points

    OK.  Thank you.

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