msp430f5308: clock jitter

We have some trouble with the stability of UCS in our MSP

We use the compare-function in a timer to generate a soundwave on a PWM

PWM-utgången har en del jitter, se bifogad bild (DISMOD_0). En halvperiod jittrar med 35 ns, på en halvperiod av 2.5 us.

The Pwm output has some jitter, in half period of 35ns of jitter in a 2.5 us halfperiod.

We tried to shut of the modulation by setting DISMOD to 1 but the jitter got worse, 220 ns.

- Is it correct that DISMOD 1 means that the modulation is turned off? With DISMOD = 1 the MOD bits in UCSCTL0 is still changing automatically.

- Is there any other way to turn the modulation off?

- Vi mätte på ACLK, P1.0-pinnen. Även den jittrar lite trots att vi har säkertställt att vi går på kristall. - We measured on the ACLK, P1.0-pin. Also this one jitters a bit despite the fact that we are running on cristal, can this be a load problem?

:

- SMCLK is drivin the PWM timern.

- We use timer B with latchad CCR values for duty-cycle.

Init sequence to UCS:

    volatile uint16_t i;

    // Stop the watchdog.

    WDTCTL = WDTPW + WDTHOLD;

    // Select clock function for the XIN and XOUT pins.

    XTAL_PORT_SEL |= (XIN_PIN | XOUT_PIN);

    // Start the XT1 oscillator.

    UCSCTL6 &= ~(XT1OFF);

    UCSCTL6 |= XCAP_3;

    // Wait for the crystal to stabilize.

    do {

        // Clear all oscillator faults.

        UCSCTL7 = 0;

        // Clear oscillator fault flag.

        SFRIFG1 &= ~OFIFG;

        for (i = 0x4800; i > 0; i--) asm("NOP");

    } while (SFRIFG1 & OFIFG);

    UCSCTL0 = 0;        // Content updated automatically in HW.

    UCSCTL1 = DCORSEL_4 // DCORSEL = 4 -> 3.2 to 12.3 MHz.

        | DISMOD;       // DISMOD = 1 -> Modulation disabled.

    UCSCTL2 = FLLD_1    // FLLD = 1 -> f_DCOCLK / 2,

        + 121;          // FLLN = 121.

    UCSCTL3 = SELREF__XT1CLK// XT1CLK as source.

        | FLLREFDIV_0;      // No FLL reference divider.

    UCSCTL4 = SELA__XT1CLK  // XT1CLK as ACLK source.

        | SELS__DCOCLK      // DCOCLK as SMCLK source.

        | SELM__DCOCLK;     // DCOCLK as MCLK source.

    UCSCTL5 = 0;            // 0: no clock divider.

    UCSCTL6 = XT1DRIVE_0    // The clock has started, the drive can be reduced.

        | XT2OFF            // No XT2 input.

        | XCAP_3;           // 12 pF capacitors.

    // Wait for DCO to synchronize with ACLK (at least 28*32 ACLK cycles)

    for (i = 0x1C00; i > 0; i--) asm("NOP");

    // Erase possible faults.

    UCSCTL7 = 0;

    // Clear the oscillator fault flag.

    SFRIFG1 &= ~OFIFG;