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Timer_A IDx Bits vs. BCM+ DIVAx, DIVSx and DIVMx Bits

Jonthornham
Expert 1490 points


I am reading about dividing clock frequencies.  I noticed the clock frequency can be adjusted in the Timer-A peripheral using the IDx bits of the TACTL register.  I also noticed it can be adjusted using the BSM+ peripheral using the BCM+ DIVAx, DIVSx and DIVMx bits of the BCSCTLx registers.  My questions is, do they accomplish the same thing and if so can they be used together to reduce the clock frequency even further?  If they are not the same thing, why would I use one over the other?

Thanks,

Jon

  • 0
    Guru 58965 points

    There are many different clocks in MSP430. I think "the clock" you are asking is the one used by TimerA for counting TAR etc.

    Your "the clock" is derived from a clock source (as selected by TASSEL) divided by 1, 2, 4, or 8 (as chosen by ID). TASSEL can select ACLK, SMCLK, etc as the clock source for TimerA.

    ACLK is XT1 clock  divide a factor as chosen by DIVA.

    SMCLK is derived from a clock selected by SELS divided by factor as chosen by DIVS.

  • 0
    TI__Guru 64610 points

    They are separate divider circuits.  In the BCM+ module, you can configure the DIVAx, DIVSx and DIVMx to generate the resulting clock frequency for ACLK, SMCLK and MCLK respectfully.  These reference clocks can then be utilized by a number of modules in the specific MSP430 device as well as brought out via pins on the device.

    Within the TimerA module, it can be configured to use 1 of the 3 device level clocks, ACLK, SMCLK and MCLK, and further divide that selected clock down via the IDx bits.

    Therefore, they worked in tandem and can be used together to further reduce the reference clock frequency used by the TimerA circuit itself.

  • 0 in reply to BrandonAzbell
    Expert 1490 points

    Thanks for the reply.  I got thinking about this while I was getting groceries.  I suppose if I were not using Timer_A then I could only divide the clock frequency by a maximum of 8 for the clock.  Do the TImer_A divisions simply allow for more variations of clock frequency?  It seems the TImer_A divisions work in addition to the BCS+ clock in use.  I also need a clock to be running to utilize the Timer_A divisions but to not need to engage the timer to use the BCS+.  I hope that's right.

    Take care,

    Jon

  • 0 in reply to old_cow_yellow
    Expert 1490 points

    Thanks old_cow_yellow.

  • 0 in reply to Jonthornham
    Guru 58965 points

    You are welcome.

    There are many different clocks in a MSP430. Many of them are selectively derived from other clocks, and often with the option of a divider factor. Each of these clocks can be used only in certain modules for certain purposes. I think you are still stuck with "the clock" use only inside TimerA. Your "the clock" is not used by the CPU. It is not used by the UART. It is not used by TimerB. It is not used by ADC. etc. etc. Changing the divider factor of "the clock" has no effect on other clocks and modules other than TimerA.

  • 0 in reply to old_cow_yellow
    Expert 1490 points

    I understand that there are different clock sources.  I also understand that the there is no specific clock used only in TImer_A.  I tried to state that but I am a newb so I must have misconstrued the message.  I was trying to state that while at the store I realize the divisions of Timer_A were for TImer_A and had no effect on the rest of the MCU.

    Thanks again,

    Jon

  • 0 in reply to Jonthornham
    Guru 227245 points

    Jon Thornham said:
    I realize the divisions of Timer_A were for TImer_A and had no effect on the rest of the MCU.

    Indeed. Many modules have additional predeviders for this or that use. Some only limited binary dividers (liek the timers), some more complex and larfger ones (like the UART baudrate divider).

    However, in the clock module you can define the divider for the oscillator, the ratio between oscilaltion frequency and the system-wide available standard clocks (MCLK/SMCLK/ACLK) So with an 8MHz crystal, you can set SMCLK/MCLK to 8MHz and ACLK to (8MHz/8 =) 1MHz if you want, giving you two system-wide available ffrequencies for all hardware modules. However, you'll likely need more (well, acutally less, in frequency) than that: 115200 for the UART, 250kHz for the I2C, 2 MHz fo the timer, 4MHz for the other timer... Hence the individual dividers in the different modules.

  • 0 in reply to Jens-Michael Gross
    Expert 1490 points

    Thanks Jens-Michael.  That's what I was assuming the thinking was.  Since we have limited clocks with potentially many functions, it made sense to be able to break down the divisions further for peripherals.  

    Take care,

    Jon

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