MSP430FR2355: Code only seems to run when I run CCS and debug???

Steve Wenner

Part Number: MSP430FR2355

Hello...

I have an MSP430FR2355 Development board....

If I import msp430fr235x_CS_03.c from resource explorer and run the code and monitor SMCLK on P1.0 I see 16MHz as expected. When I stop the debugger the clock continues....if I power the board down and up the clock comes back....ALL GOOD!

now if I load the following onto the board

SysClk_Handle_t sysClk;

#ifdef CLK_TEST
GPIO_RegDef_t *sm_a_clk_test = PORT1, *mclk_test = PORT3;
#endif

int main(void)
{
	WDTCTL = WDTPW | WDTHOLD;	// stop watchdog timer
	
    /*
     * System Clock / ACLK Configuration
     */
    sysClk.pSysClk = CLOCK;
    sysClk.SysClk_Config.Clock_MCLK = MCLK_16MHZ;
    sysClk.SysClk_Config.FLL_Source = FLL_EXT_XTL;
    sysClk.SysClk_Config.Clock_SMCLKDiv = SMCLK_DIVIDE1;
    init_Clock(&sysClk);

#ifdef CLK_TEST
    sm_a_clk_test->DIR |= BIT1 | BIT0;
    sm_a_clk_test->SEL[1] |= BIT1 | BIT0;
    mclk_test->DIR |= BIT0;
    mclk_test->SEL[0] |= BIT0;
#endif

    while(1);
}

...and hit play the clock comes up as expected to 16MHz, HOWEVER when I stop the debugger the clock flatlines and stops....If I repower the board the clock never comes up again.

Now the interesting piece....If I reflash it with the code that doesn't work the clock NEVER comes up...I first have to reflash it with msp430fr235x_CS_03.c AND RUN it. If I do this then reload my code and run I see the clock.

What is this telling me???? Is it property settings on my project???? Doesn't seem to be code because a re-flash with the so called bad code should allow the clock to show up when I run it without the need to reflash it with the demo code???

Any and all help here would be nice as I don't know what to think

Thanks

Steve

over 2 years ago

0 Steve Wenner over 2 years ago

Genius 3240 points

...more info....

I've since moved to comparing against msp430fr235x_CS_05.c which is using XT1CLK and more in line with what I want........

.._05 code clock registers:

my non working code clock registers (other than CSCTL0 (which is expected upon a pause) they all look the same):

For reference here is my driver code for setting up the clock:

void init_Clock(SysClk_Handle_t *clkConfig)
{
    GPIO_RegDef_t *p_clkXtal = PORT2;

    /*
     * depending on frequency
     * select wait states
     */
    if (clkConfig->SysClk_Config.Clock_MCLK > MCLK_8MHZ)
    {
        if (clkConfig->SysClk_Config.Clock_MCLK > MCLK_16MHZ)
            FRCTL0 = FRCTLPW | NWAITS_2;
        else
            FRCTL0 = FRCTLPW | NWAITS_1;
    }
    else
    {
        FRCTL0 = FRCTLPW;
    }
    p_clkXtal->SEL[1] = (uint16_t)((BIT6 | BIT7) << 8);

    if (clkConfig->SysClk_Config.FLL_Source == FLL_EXT_XTL)
    {
        do
        {
            clkConfig->pSysClk->CSCTL[7] &= ~(XT1OFFG | DCOFFG);  //Clear XT1 and DCO fault flag
            SFRIFG1 &= ~OFIFG;
        } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag
    }

    __bis_SR_register(SCG0);  // disable FLL
    if  (clkConfig->SysClk_Config.FLL_Source == FLL_EXT_XTL)
        //set external low freq crystal
        clkConfig->pSysClk->CSCTL[3] =  SELREF__XT1CLK;
    else
    {
        //set REFO high power > 8Mhz
        if (clkConfig->SysClk_Config.Clock_MCLK > MCLK_8MHZ)
            clkConfig->pSysClk->CSCTL[3] = SELREF__REFOCLK;
        else
        {
            //set REFO low power < 8Mhz
            clkConfig->pSysClk->CSCTL[3] = SELREF__REFOCLK | REFOLP;
            while(clkConfig->pSysClk->CSCTL[7] & REFOREADY == 0);
        }
    }

    switch (clkConfig->SysClk_Config.Clock_MCLK)
    {
    case MCLK_2MHZ:
        clkConfig->pSysClk->CSCTL[1] = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_1;
        clkConfig->pSysClk->CSCTL[2] = FLLD_0 + 60;
        break;
    case MCLK_4MHZ:
        clkConfig->pSysClk->CSCTL[1] = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_2;
        clkConfig->pSysClk->CSCTL[2] = FLLD_0 + 121;
        break;
    case MCLK_8MHZ:
        clkConfig->pSysClk->CSCTL[1] = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_3;
        clkConfig->pSysClk->CSCTL[2] = FLLD_0 + 243;
        break;
    case MCLK_12MHZ:
        clkConfig->pSysClk->CSCTL[1] = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_4;
        clkConfig->pSysClk->CSCTL[2] = FLLD_0 + 365;
        break;
    case MCLK_16MHZ:
        clkConfig->pSysClk->CSCTL[1] = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_5;
        clkConfig->pSysClk->CSCTL[2] = FLLD_0 + 487;
        break;
    case MCLK_20MHZ:
        clkConfig->pSysClk->CSCTL[1] = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_6;
        clkConfig->pSysClk->CSCTL[2] = FLLD_0 + 609;
        break;
    case MCLK_24MHZ:
        clkConfig->pSysClk->CSCTL[1] = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_7;
        clkConfig->pSysClk->CSCTL[2] = FLLD_0 + 731;
        break;
    default:
        break;
    }
    __delay_cycles(3);
    __bic_SR_register(SCG0);                     // enable FLL

    Software_Trim();
    while(clkConfig->pSysClk->CSCTL[7] & (FLLUNLOCK0 | FLLUNLOCK1));

    clkConfig->pSysClk->CSCTL[4] = SELMS__DCOCLKDIV;
    if (clkConfig->SysClk_Config.FLL_Source == FLL_INT_REF)
        clkConfig->pSysClk->CSCTL[4] |= SELA__REFOCLK;
    else
        clkConfig->pSysClk->CSCTL[4] &= ~(BIT9 | BIT8);

    switch (clkConfig->SysClk_Config.Clock_SMCLKDiv)
    {
    case SMCLK_DIVIDE1:
        break;
    case SMCLK_DIVIDE2:
        clkConfig->pSysClk->CSCTL[5] |= DIVS__2;
        break;
    case SMCLK_DIVIDE4:
        clkConfig->pSysClk->CSCTL[5] |= DIVS__4;
        break;
    case SMCLK_DIVIDE8:
        clkConfig->pSysClk->CSCTL[5] |= DIVS__8;
        break;
    default :
        break;
    }
}


static void Software_Trim(void)
{
    unsigned int oldDcoTap = 0xffff;
    unsigned int newDcoTap = 0xffff;
    unsigned int newDcoDelta = 0xffff;
    unsigned int bestDcoDelta = 0xffff;
    unsigned int csCtl0Copy = 0;
    unsigned int csCtl1Copy = 0;
    unsigned int csCtl0Read = 0;
    unsigned int csCtl1Read = 0;
    unsigned int dcoFreqTrim = 3;
    unsigned char endLoop = 0;

    do
    {
        CSCTL0 = 0x100;                         // DCO Tap = 256
        do
        {
            CSCTL7 &= ~DCOFFG;                  // Clear DCO fault flag
        }while (CSCTL7 & DCOFFG);               // Test DCO fault flag

        __delay_cycles((unsigned int)3000 * 16);// Wait FLL lock status (FLLUNLOCK) to be stable
                                                           // Suggest to wait 24 cycles of divided FLL reference clock
        while((CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)) && ((CSCTL7 & DCOFFG) == 0));

        csCtl0Read = CSCTL0;                   // Read CSCTL0
        csCtl1Read = CSCTL1;                   // Read CSCTL1

        oldDcoTap = newDcoTap;                 // Record DCOTAP value of last time
        newDcoTap = csCtl0Read & 0x01ff;       // Get DCOTAP value of this time
        dcoFreqTrim = (csCtl1Read & 0x0070)>>4;// Get DCOFTRIM value

        if(newDcoTap < 256)                    // DCOTAP < 256
        {
            newDcoDelta = 256 - newDcoTap;     // Delta value between DCPTAP and 256
            if((oldDcoTap != 0xffff) && (oldDcoTap >= 256)) // DCOTAP cross 256
                endLoop = 1;                   // Stop while loop
            else
            {
                dcoFreqTrim--;
                CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
            }
        }
        else                                   // DCOTAP >= 256
        {
            newDcoDelta = newDcoTap - 256;     // Delta value between DCPTAP and 256
            if(oldDcoTap < 256)                // DCOTAP cross 256
                endLoop = 1;                   // Stop while loop
            else
            {
                dcoFreqTrim++;
                CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
            }
        }

        if(newDcoDelta < bestDcoDelta)         // Record DCOTAP closest to 256
        {
            csCtl0Copy = csCtl0Read;
            csCtl1Copy = csCtl1Read;
            bestDcoDelta = newDcoDelta;
        }

    }while(endLoop == 0);                      // Poll until endLoop == 1

    CSCTL0 = csCtl0Copy;                       // Reload locked DCOTAP
    CSCTL1 = csCtl1Copy;                       // Reload locked DCOFTRIM
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
}

0 Amruta Deole over 2 years ago in reply to Steve Wenner

TI__Intellectual 2065 points

Hi Steve,

First, I want to clarify some things about the issues with flashing the code--when you flash the msp430fr235x_CS_03.c, the code is working but when you flash your code it is not working--and the only difference is the clock source?

+1 Steve Wenner over 2 years ago in reply to Amruta Deole

Genius 3240 points

Hello Amruta....

No the picture is somewhat changed as I experiment here....

Firstly I am now comparing AGAINST msp430fr235x_CS_05.c. (this is in line with what I want using XT1 Crystal)

I posted above to show the registers of the clock after I run the two applications (mine and ..._05.c)....

My code will work AFTER I run the ..._05 application. I can NOW run it, pause it and stop it and it continues to show me clocks at the output HOWEVER when I power my code down and start it back up it will not run. If I reflash with my code I have no luck BUT if I FLASH AND RUN the ...._05 code (the key here is I MUST RUN the ..._05 code, just flashing doesn't do it) I can then reflash with my code and I am running again

Make sense?

0 Steve Wenner over 2 years ago in reply to Steve Wenner

Genius 3240 points

Issue is resolved.....

Stupid misfire....

I never unlocked the GPIO

PM5CTL0 &= ~LOCKLPM5

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MSP430FR2355: Code only seems to run when I run CCS and debug???