Other Parts Discussed in Thread: MSP430F5529
I am having a hard time with the BSL on the MSP430F5529, specifically, regarding I/O pin state at startup after implementing my custom BSL (just to change VID/PID).
Background:
Plugging in a virgin MSP430F5529 on my custom product, the standard TI VID/PID BSL loads up. I can then use the application to update the firmware to the device image build from CCS 4.2.
Using the PUR short to 5V to get it back into the BSL still works.
Note: The 3.3V core voltage regulator has a control line from P8.2 that is active high. The pin is floating normally and does not interrupt application normally.
Problem:
When I program in the modified BSL that has the VID/PID changed plus the clock source modifications required to get it to fit, the device will no longer enumerate into the BSL using the hardware reset.
I notice that P8.2 appears to have its PREN set low, thereby dragging down the weak pull-up (10k or even a 5k) I have on the 3.3V regulator providing core voltage. I have removed all portions of the BSL in an attempt to eliminate PREN from getting set and have tried to drive it high without any satisfactory results.
Second Problem:
I then tried to restore the original BSL using SLAA450 BSL image BSL.00.03.83.33.d43 with IAR KickStart (Assembler/Compiler v. 5.20.1) with a "Download->File" method and the same problem exists with P8.2 appearing to have its pull-down resistor enabled.
I was wondering if anyone has seen this problem and if there is a solution without having to re-spin our board.
In the meantime, I will go back to the 5529 Eval board and see if the BSL behaves any differently when the core voltage is not in any way controlled by the micro.