What am I missing?
Using the msp430g2x21_usi_02.c SPI full-Duplex 3-wire Master demo code from 'slac463.zip', I am always getting 9 SCLK clocks on the first SPI transfer, then the expected 8 SCLK clocks on subsequent SPI transfers when I configure the USI Clock phase select USICKPH to a '1' in the USICTL1 register. This occurs with either setting of the clock polarity (USICKPL in the USICKCTL register).
My environment:
- Code Composer Studio Core Edition Version: 4.2.3.00004
- MSP-EXP430G2 LaunchPad Experimenter Boards
- MSP430G2231 processor
The following is some code to demonstrate the issue: (derived from msp430g2x21_usi_02.c)
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
USICTL0 = USISWRST; // USI reset for configuration
USICTL0 |= USIPE7 + USIPE6 + USIPE5 + USIMST + USIOE; // Port enable, SPI master
USICTL1 |= USICKPH; // capture/change <<==========================
USICKCTL = USIDIV_4 + USISSEL_2; // /16 SMCLK, USICKPL = inactive lo
USICTL0 &= ~USISWRST; // USI released for operation
USISRL = 0x10; // load initial data
USICNT = 8; // start transfer
_delay_cycles(200); // wait
USISRL = 0x20; // load more data
USICNT = 8; // start another transfer
LPM0; // Enter LPM0
}
The following shows the results on an anyalzer:
As shown, the first transfer has 9 SCK clocks while the second transfer has the expected 8 SCK clocks.
Only 8 SCK clocks were expected for the first transfer as shown in the following:
The only difference between these two examples are the second does not have the USICKPH bit set in the USICTL1 register.
Am I missing something in the configuration of the USI for SPI mode?
I have tried another MSP430G2231 with the same results.
Thanks,
Dan
