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MSP430FR5969: DMA with ADC to work around Errata ADC43

Part Number: MSP430FR5969

Hi there,

I was trying to use DMA to transfer ADC samples from three channel into one Array in a format of {ADC channel 0_Sample0, ADC channel 1_Sample0,  ADC channel 2_Sample0, ADC channel 0_Sample1, ADC channel 1_Sample1,  ADC channel 2_Sample1,  ......}

Noticing the Errata 43 and I tried to use to DMA to achieve that, first one for fix to block with the size of Array, and the other one for changing the source address in a loop of 3. ie: {0x0860, 0x0862, 0x0864}

But for my case, it never work. Even though that in debug session I saw the SA register of first DMA channel was actually updated to the value I wanted, but the data moved to Array is always from the ADC channel set in the DMA init process.

That means once DMA is set up, it would not take the value in DMAxSA or DMAxDA anymore. And I found that statement in User Manual Chapter 11.2.2.2 saying "The DMAxSA, DMAxDA, DMAxSZ registers are copied into temporary registers....."

So I just wonder how the guys achieve these in their project by using two DMA.

 

BR,

Jason

  • Hi Jason

    Please consider avoid ADC43 by using 00b = Single-channel, single-conversion or 10b = Repeat-single-channel on ADC12CONSEQx of ADC12CTL1 Register.

    Thanks!

  • But I need to sample three channels at same sampling rate. I have to use Sequence of channels mode. Any other advise?

  • Hi Jason 

    May I know if you can accept handle ADC conversion data by software instead of DMA?

    Thanks!

  • As I read ADC43, it says you will get 3 triggers for each sequence, rather than the 1 trigger as suggested by User Guide (SLAU367P) Sec 11.2.11. 

    The recommendation is to Not use a Block transfer (DMADT=1) of 3 words, but rather a Single transfer (DMADT=0) of 3 words. Single transfer means one (word) transfer per trigger, so the 3 triggers will transfer the entire sequence. 

    How are you configuring the DMA?

    [Edit: Minor clarification.]

  • Hi Xiaodong,

    I prefer to keep as much work in background as possible.

    Thanks

  • Hi Bruce,

    In the way you suggested I could only get a data format {ADC channel 0_Sample0, ADC channel 1_Sample0,  ADC channel 2_Sample0}

    But I prefer it can fill up a 510 long array rolling the data from three channel. 

    {ADC channel 0_Sample0, ADC channel 1_Sample0,  ADC channel 2_Sample0, ADC channel 0_Sample1, ADC channel 1_Sample1,  ADC channel 2_Sample1,  ......ADC channel 0_Sample169, ADC channel 1_Sample169,  ADC channel 2_Sample169}

    Any advice on that? Appreciated.

    Jason

  • I think I see what you have in mind now. It's not clear to me how the method described in the other thread would work, since (a) as you observed, the SA/DA/SZ registers can't be changed while the DMA channel is active (DMAEN=1) and (b) the DMA can step through the MEMx register array (0x860-0x864) quite easily (with DMADT=0). Maybe there's something I'm missing?

    The annoyance from ADC43 is that with Single mode you need to have the DMA increment both the Source and Destination addresses, but with different moduli (3 vs 510). A Block transfer (which you can't use) wouldn't increment the Source, and so could be used repeatedly. (Perhaps that was what Ryan was saying in the other thread.) 

    If your goal is to collect the data with no CPU intervention, keep in mind that with CONSEQ=1 each ADC burst must be followed by toggling ENC (=0, then =1) to enable the next burst [Ref User Guide (SLAU367P) Sec 34.2.8.2], so the CPU will have to intervene for each burst in any case. Once you've taken the (DMA) interrupt to toggle ENC, it's a small addition to update the DA (to move through your array) and re-enable the channel.

    You mentioned needing fixed-rate sampling (I'm supposing you're using a timer), but a separable question is whether you need the conversion bursts to be (quasi-)simultaneous across the channels; in some applications I want the former but don't really care about the latter. If this is your case, you might try using CONSEQ=3 with MSC=0, and tripling your trigger rate. This provides fixed-rate for each channel, but the channels in the sequence are offset by 1/3rd of the period. With CONSEQ=3 there is no need to toggle ADC12ENC between cycles. Since the bursts are then self-paced, you can consider using the entire ADC12MEMx array as a DMA Source. This would give you 32/3=10 channel cycles between interventions, which isn't 170 but it's something.

  • Thanks. In the end I have to reset destination address after each sampling sequence is finished. But I think it is the only way for my scenario.

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