MSP430F47187: MCLK has jitter around 11%

When FLL is enabled and achieved the DCOCLK usually switches automatically between two different frequencies. The goal of the FLL is so that the average frequency over any consecutive 32 cycles of DCOCLK is as close to the desired multiple of the reference as possible. In doing so, it “jitters” between two steps of adjacent MODx settings in a predictable way. According to the data-sheet (slas626C.pdf) page 40, the step size, Sn, between adjacent DCO taps can be anywhere from 6% to 17%.

If you do not want DCOCLK to “jitter”, you may disable the FLL and set the MODx bits to all 0’s. But you will have very limited choices of the DCOCLK frequencies and they depend on operating temperature and voltage.

Dear old_cow_yellow,

I did not know how to choose FN before. SCIF0 register explanation in the user manual seems not enough. (Or I can say it is not correct)

In the datasheet, given FN table is different. In our design VDD is around 3.45V and I need 8 MHz. If I choose FN_2, there is possibility to get failure. Because, even with the max tab, it might not reach to 8 MHz. So for the jitter also, it is good to maximize FN as much as possible. Because lower tabs (between 1-20) have more precision.

Tomorrow, I will check current tabs, and try to reduce them by choosing higher FNs.

Thanks.

Hi,

Today I did a test by disabling FLL loop. ( _BIS_SR(SCG0); )

With FN_4 and DCOtab=11 and MOD = 0, I measured MCLK is 7.89 Mhz

With FN_4 and DCOtab=12 and MOD = 0, I measured MCLK is 8.56 Mhz

Well, my target is 8.00 Mhz. From datasheet explanation, I used that equation to solve MOD to get my target frequency:

[ f_dco _tab*(32-MOD) + f_dco _tab1*(MOD) ] / 32 = Target Frequency

For my case f_dco _tab = 7.89

f_dco _tab1 = 8.56 (this is DCO tab+1)

and Target is 8.00Mhz.

When I solved the equation I found MOD should be 5.25, so the closest integer 5 I chose. With 5 expected frequency is 7.994 Mhz which is fine.

The test result was fine, I measured frequency around 8 Mhz and jitter is only about 7%.

But my question, why does MSP FLL loop have more jitter than 7%? It seems during operation, MSP changes the DCO tabs more than one step. This shouldn't be required. Why do you think?

Thanks.

I do not know how they designed the FLL.

This is my pure speculation. When they detected that MOD should be 5.25, they set MOD to 5 most of the time (~3/4) and change MOD to 6 some of the time (~1/4). This resulted in better average but wrose jitter.

Could you try D=4? That is, make DCOCLK=32MHz resulting a MCLK=8MHz. The jitter could be smaller.

BasePointer said:

But my question, why does MSP FLL loop have more jitter than 7%

Besides this, OCY i sright: overclockign the DCO and use a divider averages 2 or 4 DCO cycles, so the average jitter will be by a factor 2 to 4 smaller. (and since modulation has an evenly distribution of the two frequencies, the maximum jitter won't be noticeably higher than the average jitter)

BasePointer said:

It seems during operation, MSP changes the DCO tabs more than one step.

Hi,

I've just understood the functionality of FLL Divider.

My application is battery powered and VDD of MSP can vary between 2.3V and 3.5V

For these conditions, I couldn’t find proper FN option to get 8 MHz without DCO failure.

If DCOPLUS=1, here are the conditions I have to fit:

@2.3V Min DCO_tab₂₇ frequency should be greater than MCLK asked * D for the chosen FN

@3.5V Max DCO_tab₂ frequency should be less than MCLK asked * D for the chosen FN

Let’s suppose we chose D=4 with DCOPLUS=0 to decrease jitter by averaging. In that case, we need fDCO = 32 Mhz. Even with FN_8 option, @2.2V Min DCO_tab₂₇ = 21 MHz so highly possible to get DCO failure.

How are you choosing FN value?

Or are you using some smart code inside oscillator failure interrupt?

Thanks.

BasePointer said:

are you using some smart code inside oscillator failure interrupt?

However, using a divider of 2, going for 16MHz DCO clock, will work in FN_8 for full operating voltage range.

Jens-Michael Gross said:

However, using a divider of 2, going for 16MHz DCO clock, will work in FN_8 for full operating voltage range.

With the options FN_8, D = 2 and DCOPLUS = 0, we need 16Mhz at DCO output to get 8Mhz in MCLK. This configuration seems OK for FN, it covers all the VDD range required. But that time problem is N. We need a value decimal 244 for N which is not possible. N has only 7 bits.

BasePointer said:

With the options FN_8, D = 2 and DCOPLUS = 0, we need 16Mhz at DCO output to get 8Mhz in MCLK. This configuration seems OK for FN, it covers all the VDD range required. But that time problem is N. We need a value decimal 244 for N which is not possible. N has only 7 bits.

So all you can do is going for DCOPLUS=1 and D=2 and N=122. Then FN_4 or FN_3 are fine. You don't have any jitter smoothing then, of course.

Looks like this MSP is not the optimum device for low-jitter 8MHz DCO operation :)

This was the first project that we met with MSP430 family. Comparing to competitors like microchip, freescale, st, I saw that it has very bad design for clocking system such as its FLL module, no LCD without ACLK, silicon bugs for low power crystals, mass productions problems like historical fusing method, and bad one they try to provide their limitations as if it was a feature.. bad support, ti technical team usually returns minimum within 3 weeks with a non helpful content. Only place we take support is here and sometimes not enough. We have chosen it by thinking it was cheap. But as a result, to design a robust product with it, this msp needs one external wdt, one external high frequency crystal beside low frequency one, two voltage detector for batteries (because of limited svs capabilities and no general purpose adc) But at the beginning, ti team said they could cover all our requirements.

Anyway, thanks for your help.

The 5x family has been improved much (greatly improved clock system, internal 32kHz oscillator and much more), yet if you need the LCD driver, then you're stuck with the 4x family.
I started with the 1x family and we still use it in most of our projects and it does the job. Yes, external highspeed crystal and for some applicaitons a low-speed is necessary, but then this is much more precise than any internal solution (including the competitors). But on the bottom line it is way better and easier to handle than the (cheaper) PICs and slimmer and cheaper than the ATMega chips of comparable power. And we started with the free MSPGCC compiler, so our total beginning costs were ~$25 for a parallel FET. The serial FET for the ATMega128 (which we also use) wa sway more expensive, not to count the PIC programmer and the PIC compiler for the early PIC-based projects. So we're quite content with the MSPs.