MSP430F2272: MSP430F2272 POR

yamamoto chinatsu

Part Number: MSP430F2272

How many seconds should I wait between the rise of VCC and the rise of RESET?

Currently, the reset signal is only Pull-Up, so it rises as soon as the power is turned on.
If it is only Pull-Up, it takes 290 nsec from the rise of VCC to the rise of RESET.
In this state, the MCU will fail to start up in 20% of the cases. (Tried 10 times, failed 2 times)

Adding a capacitor of 4.7uF to the reset signal line results in a delay time of 83msec.
In this condition, the MCU will surely boot successfully.

I am unable to find from the datasheet how many seconds to wait between the rising edge of VCC and the rising edge of RESET.
If there is a page in the datasheet or user manual that defines this, please let me know.

Thanks.

over 2 years ago

0 Susan Moore over 2 years ago

TI__Expert 4990 points

Hello,

For information on POR and RESET, please look at Chapter 2: System Resets, Interrupts, and Operating Modes of the MSP430F2xx, MSP430G2xx Family User's Guide.

Thank you,

Susan

0 yamamoto chinatsu over 2 years ago in reply to Susan Moore

Prodigy 10 points

Thanks for your reply.

Is there any mention of the reset signal pulse width? Or as this table shows, if I set the RESET pin to 47kΩ pullup and 2.2nF pulldown, does it matter?

0 Susan Moore over 2 years ago in reply to yamamoto chinatsu

TI__Expert 4990 points

Hello,

At power-up, the RST/NMI pin is configured to the reset state. In the reset state, the CPU is held in reset as long as the RST/NMI pin is held low. If you are not using the pin, please set the 47kΩ pullup and the 2.2nF pulldown (following the instructions for connections of unused pins).

In addition, Table 3-14. Interrupt and Reset Cycles in the TRM shows how many cycles of the clock a reset takes.

Thank you,

Susan

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MSP430F2272: MSP430F2272 POR