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MSP430FR6007: USART receive interrupt delayed

Part Number: MSP430FR6007

Environment:  msp430FR6007 and CCS 12.0.000009 and using ‘c’

 

6007 is running with 1 wait state.  USART is running at 57.6 kbps.

 

Only two interrupts turned on:  USART A0 and TimerA0.  Timer is set for about 1ms.

 

When sending an async stream to the 6007, the interrupt for receive occurs after nearly 800 us rather than fairly quickly (fairly quick expected).  I attach the output of a logic analyzer (pdf) showing the problem.

 

In the picture, T4 is a pulse put out in the first couple of instructions in the USART interrupt routine.  Similarly, T7 is a pulse put out in the first couple of instructions in the Timer interrupt routing.

 

You can see the first USART int occurs at about 900 us after the character is received.  Thereafter, they occur quickly after the receipt of the character.

 

I have to admit I am stumped.  Please help.  I gotta be doing something wrong somewhere.

 

Regards

Bob Scott

bobscott@jamesport.com

214.673.1439 

 

 Scan230717100508.pdf

  • The usual reason for a delayed entry into an interrupt service routine is that there is another one running. Global interrupts (GIE) are disabled on entry to an ISR.

    You can of course enable interrupts within the ISR but only with great care to avoid trouble.

    It appears that the timer tick coincident with that first delayed UART tick is also delayed. So look at the timer ISR.

  • The signal T7 is set at the start of the timer isr and reset at the end.  I have looked at every thing I can think of and have not found another isr running at that timel  Help!!!  thus the timer isr is not running during the time in question.  help!!!

  • Can you check: why the timer interrupt seems to be different?

    What about you remove everthing and only remain the UART transmtion function?

  • OK.  Found it. A totally dumb a** mistake on my part.  Bad condition test in the front part of the USART int routine and it was getting hung up there.  It should not even go into that part of the int routine but it was.  The logic analyzer pulse only covered the receive portion of the int routine.  When the analyzer is changed to cover the entire routine, the problem becomes very apparent.

     

    Don’t have it fixed yet, but it should be easy now that I know what the problem really is

     

    Many thanks four your help.  Problem found.

     

    Regards

    Bob Scott

    bobscott@jamesport.com

    214.673.1439 

     

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