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MSP430FR5994: Fixing the ADC Sampling Rate

Christopher Wahl
Prodigy 10 points

Part Number: MSP430FR5994

Hello, 

I'm using the MSP430FR5994 and I need to sample a signal at a 10 to 100kHz sampling rate. Is there a controlled way to do this with the built-in "Repeat Single Channel Mode" (I saw it takes 14 to 15 ADC clock cycles per sample)? Or is the better way to do this by doing a single-shot conversion, and simply delaying the MSP by 1 / fs?

Thank you,

Chris

  • 0
    TI__Genius 10835 points

    Hi Chris,

    The timing for ADC consists of sample time and conversion time. 

    1) Control bit ADC12SHP defines the sample-timing method.

    2) ADC conversion requires 10, 12, and 14 ADC12CLK cycles.

  • 0
    Guru 102835 points

    For fixed rate sampling, I recommend using a timer to trigger the conversions, using ADC12SHS > 0. The possible timer triggers are listed in data sheet (SLASE54D) Table 9-18.

    The notion is to configure a timer to generate an output signal (CCRn with Up mode and OUTMOD=7 or =4) with a period corresponding to your sampling period, where a rising edge serves as SAMPCON to trigger the conversion. (Typically you would use ADC12SHP=1, but for unusual cases you can trigger both SAMPCON edges (SHP=0) with the timer.)

    For your application I suggest using CONSEQ=2 with MSC=0 [Ref User Guide (SLAU367P) Sec 34.2.8.3], since that way you don't need to toggle ADC12ENC after each conversion and so can easily use DMA.

    [Edit: Minor clarification]

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