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MSP430 F149 question from spi

Chuang Shang Yi
Prodigy 10 points
Other Parts Discussed in Thread: MSP430F149

 

;

;                                MSP430F149

;                             -----------------

;                        /|\|                       XIN|-

;                       --|RST            XOUT|-

;                         |                               |

;             LED <-|P1.0              P3.1|-> Data Out (SIMO0)

;                         |                               |

;        Scope <-|P3.4               P3.2|<- Data In (SOMI0)

;                         |                               |

; Slave  RST <-|P3.5               P3.3|-> Serial Clock Out (UCLK)

;

;   Z. Albus

;   Texas Instruments Inc.

;   Feb 2005

;   Built with IAR Embedded Workbench Version: 3.21A

;******************************************************************************

#include  <msp430x14x.h>

 

#define      MST_Data   R6

#define      SLV_Data   R7

 

;-----------------------------------------------------------------------------

            ORG     0F000h                  ; Program Reset

;-----------------------------------------------------------------------------

RESET       mov.w   #0A00h,SP               ; Initialize stackpointer

StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop watchdog timer

SetupP1     mov.b   #000h,&P1OUT            ; P1.0 setup for LED output

            bis.b   #001h,&P1DIR            ;

SetupP3     bis.b   #00Eh,&P3SEL            ; P3.1,2,3 SPI option select

            mov.b   #020h,&P3OUT            ; P3.4 setup for scope trigger and

            bis.b   #030h,&P3DIR            ; P3.5 for slave initialize

SetupSPI    mov.b   #CHAR+SYNC+MM+SWRST,&U0CTL ; 8-bit, SPI, Master

            bis.b   #CKPL+SSEL1+STC,&U0TCTL ; Polarity, SMCLK, 3-wire

            mov.b   #002h,&U0BR0            ; SPICLK = SMCLK/2

            mov.b   #000h,&U0BR1            ;

            mov.b   #000h,&U0MCTL           ;

            bis.b   #USPIE0,&ME1            ; Module enable

            bic.b   #SWRST,&U0CTL           ; SPI enable

            bis.b   #URXIE0,&IE1            ; Recieve interrupt enable

                                            ;

Init_Slave  bic.b   #020h,&P3OUT            ; Toggle P3.5: reset slave

            bis.b   #020h,&P3OUT            ;

Wait        mov.w   #050000,R15             ; Delay to R15

L1          dec.w   R15                     ; Decrement R15

            jnz     L1                      ; Delay over?

                                            ;

            mov.b   #000h,MST_Data          ;

            mov.b   #0FFh,SLV_Data          ;

                                            ;

Mainloop    mov.b   MST_Data,&TXBUF0        ; Transmit first character

            bis.b   #LPM0+GIE,SR            ; CPU off, enable interrupts

            nop                             ; Required for debugger only

                                            ;

;------------------------------------------------------------------------------

USART0RX_ISR;       Test for valid RX and TX character

;------------------------------------------------------------------------------

            xor.b   #010h,&P3OUT            ; XOR P3.4 for scope trigger

TX1         bit.b   #UTXIFG0,&IFG1          ; USART0 TX buffer ready?

            jz      TX1                     ; Jump is TX buffer not ready

            cmp.b   SLV_Data,&RXBUF0        ; Test for correct character RX'd

            jeq     PASS                    ;

FAIL        mov.b   MST_Data,&TXBUF0        ;

            bis.b   #001h,&P1OUT            ; Set P1.0 indicating data error

            reti                            ; Exit ISR

PASS        inc.b   MST_Data                ;

            dec.b   SLV_Data                ;

            mov.b   MST_Data,&TXBUF0        ;

            bis.b   #001h,&P1OUT            ; Pulse P1.0 indicating valid data

            bic.b   #001h,&P1OUT            ;

            reti                            ; Exit ISR

                                            ;

;------------------------------------------------------------------------------

;           Interrupt Vectors

;------------------------------------------------------------------------------

            ORG     0FFFEh                  ;

            DW      RESET                   ; POR, ext. Reset, Watchdog

            ORG     0FFF2h                  ;

            DW      USART0RX_ISR            ; USART0 receive

            END                             ;

 

 

This code from TI which I have some questions.

First how to check RXBUF0 and TXBUF0  is it associated with the SIMO ?

Second I use the oscilloscope to observe P3.3(UCLK) frequencyis 370KHZ i guess the frequency500KHZ because SMLK/2 ->1M/2=500KHZ but 370KHZ and 500KHZ  much worse?

Third   I use the oscilloscope to observe P3.1 frequency is 15KHZ why and  I use the oscilloscope to observe P3.4   frequency is 8KHZ  how do i know it  from this code

 

  • Guru 227245 points

    Chuang Shang Yi said:
    First how to check RXBUF0 and TXBUF0  is it associated with the SIMO ?


    RXBUF0 and TXBUF0 are the buffered input and output registers of the USART module 0. Whether TXBUF0 is empty (ready to have ew data written into it) or RXBUF0 is filled (a byte has been received) is signalled by the RXIFG and TXIFG bits which trigger an interrupt (if enabled) or can be checked by software.

    In the above code,  "bis.b   #URXIE0,&IE1"enables the interrupt for a filled RXBUF0. So as soon as a byte has been received, he processor will call teh ISR, which is (in the Interrupt vectors table) has been defined ot be the USARTRX_ISR function.

    This ISR manually checks UTXIFG0 (wait loop). Since data in and out are synchronized, TXBUF0 is usually empty as soon as RXBUF0 is filled. So this cehck is (in this code) is superfluous. And otherwise, busy-waiting loops inside ISRs are a no-go anyway.

    Chuang Shang Yi said:
    i guess the frequency500KHZ because SMLK/2 ->1M/2=500KHZ

    Where did you get the 1MHz? On the 1x series, the default frequency is somewhere in the range from 600 to 900kHz, on 3V typically 750kHz and less for higher voltage. So 370kHz fits perfectly.

    Chuang Shang Yi said:
     I use the oscilloscope to observe P3.1 frequency is 15KHZ

    Is it? I'm surprised. In this weird code, the R6 register (aka MST_Data) is 0x00, so the output on the SIMO line will be always 0. The frequency on P3.1 should be 0. And P3.4 is only changed once after program start. If you're observing a frequency on it, then it seems that your MSP is resettign with 8kHz frequency? Doesn't sound likely. Strange.

    However, the whole code has a big problem: clocking the SPI with SMCLK/2 = MCLK/2 means that you have only 16 CPU clock cycles per byte for an uninterrupted transfer. (or 2 cycles if you wait for the RXIFG bit before you begin to act).  The ISR, including the ISR latency time, is MUCH longer than that. So you're only seeing single bytes sent with 370kHz with (relatively) large gaps between them.
    It is possible that after a transfer is done, the SOMI pin switches to input or high, so with the gap between bytes, this would explain the 15kHz you're observing. This is the byte frequency : 21.6µs byte transfer, then 45µs gap due to the slow ISR. Results in 15kHz turnaround frequency.

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