Both XT1 and XT2 pins are also general I/O pins. Unified Clock System (UCS) SLAU390F–August 2012–Revised March 2018 states that on reset XT1 comes in in low frequency mode and is selected as the clock source. In the same section it states that clock pins that also can be I/O power up as I/O pins. So which is it? I assume it must be XT1 as clock source and in LF mode. Poor design because it forces me to use two clock sources when I only need a HF source.
1.2 UCS Operation After a PUC, the UCS module default configuration is: • XT1 in LF mode is selected as the oscillator source for XT1CLK. XT1CLK is selected for ACLK. • DCOCLKDIV is selected for MCLK. • DCOCLKDIV is selected for SMCLK. • FLL operation is enabled and XT1CLK is selected as the FLL reference clock, FLLREFCLK. • On devices that have XIN and XOUT shared with general-purpose I/O, XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are configured for XT1 operation. If XIN and XOUT are not shared with general-purpose I/Os, XT1 is enabled. • When available, XT2IN and XT2OUT pins are set to general-purpose I/Os and XT2 is disabled. As previously stated, FLL operation with XT1 is selected by default. If the crystal pins (XIN, XOUT) are shared with general-purpose I/Os, XT1 remains disabled until the PxSEL bits associated with the crystal pins are set. If XIN and XOUT are not shared with general-purpose I/O, XT1 is enabled. When a 32768- Hz crystal is used for XT1CLK, the fault control logic immediately causes ACLK to be sourced by the REFOCLK, because XT1 is not stable immediately (see Section 1.2.12). When crystal start-up is obtained and settled, the FLL stabilizes MCLK and SMCLK to 1.048576 MHz and fDCO = 2.097152 MHz. Status register control bits (SCG0, SCG1, OSCOFF, and CPUOFF) configure the operating modes and enable or disable portions of the UCS module (see the SYS chapter). Registers UCSCTL0 through UCSCTL8 configure the UCS module. The UCS module can be configured or reconfigured by software at any time during program execution. NOTE: For devices using RTC_B, RTC_C, or RTC_D (RTC modules that support LPM3.5), setting bit RTCHOLD = 0 in register RTCCTL1 also enables XT1, independent from UCS configuration
