Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 79 subscribers
  • Views 348 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430G2553: SPI clock not go to low after last bit.

Serghei Plamadeala
Intellectual 450 points
Part Number: MSP430G2553

configuration:

UCB0CTL1 |= UCSWRST;

P1SEL |= SIMO + SOMI + CLK;
P1SEL2 |= SIMO + SOMI + CLK;

UCB0CTL0 = UCMST; //Master mode select
UCB0CTL0 |= UCSYNC; //syncron mode
UCB0CTL0 |= UCMSB; //MSB firs
UCB0CTL0 |= UCCKPH; //Clock Phase inactive state is low
//UCB0CTL0 |= UCCKPL; //The inactive state is high
UCB0CTL1 |= UCSSEL_3; //10b = SMCLK
UCB0BR0 = 16; //low byte
UCB0BR1 = 0; //high byte
IFG2 &= ~UCB0TXIFG;
IFG2 &= ~UCB0RXIFG;

UCB0CTL1 &= ~UCSWRST;

Green CLK
blue - Data/Code for nokia 5110 display
purple is data


tek00418.png is first byte

tek00425.png is last byte

Problem is not considering nokia 5110 clock for 8th bit if remain to high and not considering last 8bytes valid.

If i write again 8 bits the validation of previous 8bit will considering, but not current last 8bit Slight smile.

transmitting: 1st Byte(not considering anything's on display); 2nd Byte(appear on 5110 1st data byte); 3st Byte(appear on 5110 2nd data byte)...

If I put Brake Point and reset Cip Select for CLK (Port1 Bit5), CLK is going to low and appear last Byte data on display.

Can you propose any solution?

Thanks

  • 0
    Intellectual 450 points

    I tried any combination below: and not work.
    UCB0CTL0 |= UCCKPH; //Clock Phase inactive state is low
    .UCB0CTL0 |= UCCKPL; //The inactive state is high

    Not respecting UCKPH1 and UCKPL 0 on the end to going to low.
     
    MSP430F2xx, MSP430G2xx Family User's Guide (Rev. K)(www.ti.com/.../slau144k.pdf

  • 0 in reply to Serghei Plamadeala
    Guru 21505 points

    This reminds me of when I was trying to get one of those cute little OLED displays to work over SPI with a F2553. The clock phase and polarity settings I chose should have worked since the data sheet didn't show any preference for the idle state of the clock. It did care. After trying each of the four choices I found that only one worked. Which happens to be what you are using.

    Digging up a data sheet for the 5110 I see that it says it samples data on the rising edge of the clock. Try CLKPH=0 and CLKPL=1

  • 0 in reply to David Schultz
    Intellectual 450 points

    don't meter, after last bit should go again to low according data sheet with CLKPH=1 and CLKPL=0

  • 0 in reply to Serghei Plamadeala
    TI__Genius 13885 points

    Hi Serghei,

    As you described. If you closed the CS signal (set low), and then the CLK polarity is low after last bit, but if CS keep high, then the CK is keep high. Am I right?

    As for this, what is the CLK status after the last bit transferred without connected to 5110? I want to make sure that it is not the slave makes the impact on the CLK line.

    B.R.

    Sal

**Attention** This is a public forum