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MSP430F6769A: How to set MCLK and SMCLK

toshiharu.yoshie
Prodigy 90 points
Part Number: MSP430F6769A


Hi,

Thank you for always teaching me!

Please tell me about the frequency settings.

When using SD24_B, the source frequency was set to SMCLK. However, when I looked at the User's Guide, I thought that the default setting was 1.048576 MHz.

www.ti.com/.../slau208q.pdf

"When crystal start-up is obtained and settled, the FLL stabilizes MCLK and SMCLK to 1.048576 MHz and fDCO = 2.097152 MHz."（5.2 UCS Operation）

I'm thinking of setting SMCLK, wondering if increasing the frequency will make a difference in AD conversion.

Initially, I thought that MCLK and SMCLK output the maximum frequency of 25MHz.

Therefore, I am currently creating a program using CCS12.5.0.

Attached is part of the program.

It just doesn't work. In the current program, I intended to set it to about 25MHz, but when I start it through debugging, it stops at the watchdog timer.

This seems to occur when setting DCO and DCORSEL at the same time.

Since it was stated that an appropriate range must be determined in order to generate a stable frequency, the values for DCORSEL, DCO, and MOD were determined. Since the desired frequency is approximately 25MHz, I intended to set DCORSELx = 4, DCOx = 31, MODx = 0, but it did not work.

https://www.ti.com/jp/lit/ds/symlink/msp430f6769a.pdf?ts=1701143243701&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252Fja-jp%252FMSP430F6769A

（5.8.2 Clock Specifications, Table 5-5. DCO Frequency）

I think I'm using the wrong frequency setting program or setting the frequency range incorrectly, but I can't decide.

Could someone please enlighten me?

Thank you.

Toshiharu

  • 0
    TI__Mastermind 46765 points

    Hi,

    I think you can refer to this code example for setting the DCO as 25MHz. https://dev.ti.com/tirex/explore/node?node=A__APRsKIF6eDDJCIGtdBDnHw__msp430ware__IOGqZri__LATEST&placeholder=true

    However, when using SD24, it is not recommended to change the MCLK clock frequency higher than 1.048576 MHz. It could cause other issues. 

    Best regards,

    Cash Hao

  • 0 in reply to Cash Hao11
    Prodigy 90 points

    Hi, Cash

    Thank you for always answering! It's been a great help!

    Thank you for the sample code as well. For reference only.

    Cash Hao11 said:
    However, when using SD24, it is not recommended to change the MCLK clock frequency higher than 1.048576 MHz. It could cause other issues. 

    Does this mean that MCLK (or SMCLK) needs to be set to the default 1.048576 MHz, or a method of dividing MCLK raised in the sample code?

    The maximum frequency used for SD24The reason why I want to change the frequency of the SD24 is because I want to see what kind of results I get by changing the sample frequency. OSR is set to 1024. The results obtained by changing the OSR were that 1024 was the best. is 1.048576 MHz, and will it be divided into SMCLK/2, SMCLK/4, etc.? If you want to make it more detailed, divide the frequency created with the sample code and create frequencies below 1.048576 MHz.

    I am very sorry if it is difficult to convey.

    Thank you.

    Toshiharu

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