MSP430F5438A: What is state of UCBUSY while UCAxTXBUF is empty but byte is still being shifted out in UART mode.

Ref SLAU208Q,  p961:

The documentation does not specify clearly and unambiguously what UCBUSY is supposed to do; it merely says:

USCI busy. This bit indicates if a transmit or receive operation is in progress.
0b = USCI inactive
1b = USCI transmitting or receiving

In forum topic, https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/187077/last-byte-in-uart-communication-msp430, Jens-Michael Gross states, "The 2274s USCI module has an UCBUSY bit in UCA0STAT. it is clear when the chip is currently neitehr sending nor receiving. it gets immediately set if a start bit edge is detected or if you write to TXBUF, and clears when the transfer is completed. However, if the bit is set, you don't know whether it is because of receiving or sending (in case you did send something). UCA0TXIFG won't help, as it is set even if the last byte is still underways.

Questions:

1. In the above comment, what is the definition of "transfer is competed" in terms of transmit?
2. If there are no new bytes being written to TXBUF once it becomes empty, when does UCBUSY become zero?  After the stop bit?  Some time after?  What is the precise timing?
3. If no further bytes are written TXBUF, is it safe to assume that the only reason for UCBUSY becoming set again is due to a start bit detected on RXD?
4. The above comment also states, "it gets immediately set if a start bit edge is detected."  This leads me to the question: May UCBUSY be set if an incoming glitch occurs (i.e. incoming pulse shorter than deglitch time tT?  If so, how long does UCBUSY remain set?  For the duration of the glitch pulse?  Some time after?