• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 81 subscribers
  • Views 809 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How to make timer lower priority interrupt

Jim Young
Prodigy 30 points
Other Parts Discussed in Thread: MSP430F2132

I see there are a couple interrupts with priority of 17 & 16.  Are those software interrupts?  If yes, how do you "throw" them?  Would it be possible to throw one of those software interrupts in a timer interrupt so that they run after the timer interrupt exits?  If not, is it possible to have the timer interrupt start code that is lower priority than all interrupts and then exit?

I am new to microcontroller programming.

  • 0
    TI__Guru 64610 points

    What specific device are you referencing?  Also, please cite any software that you are using.

  • 0 in reply to BrandonAzbell
    Prodigy 30 points

    msp430F2132

    Code Composer 4.

  • 0
    TI__Guru 64610 points

    Jim Young said:

    I see there are a couple interrupts with priority of 17 & 16.  Are those software interrupts?

    No, these are simply unused.  Section 2.2.4 of the MSP430x2xx Family User's Guide (SLAU144) indicates unassigned interrupt vectors can be used for regular program code if necessary.

     

    Jim Young said:

    If not, is it possible to have the timer interrupt start code that is lower priority than all interrupts and then exit?

    Yes, through some means like a semaphore.  However, after the timer interrupt service routine returns and re-enables interrupts, if a higher priority interrupt is pending at that time, it's interrupt service routine will be executed.

  • 0
    Guru 58965 points

    The "interrupt priority" of MSP430 is relevant only at the moment of granting an interrupt. Once an interrupt is granted, GIE is automatically cleared.  Unless the ISR specifically sets GIE, it will not be interrupted by any mask-able interrupts no mater what the priority is.

    I occasionally use ISR that sets GIE after the "critical part" is done so that the non-critical part can be interrupted by mask-able interrupts. But this method has to be used with caution. Sometimes, the ISR may need to be re-entrant. If Timer ISR is the only one that does this, it may do what you wanted. But if you have more than one ISR that do this, the latest granted ISR will be completed first and the earliest granted ISR will be completed last. (Late birds get the worm, early birds only get left-overs.)

  • 0 in reply to old_cow_yellow
    Prodigy 30 points

    I think I found a way to do what I need to do.  I set a flag in the timer ISR indicating to the main routine that I need to do something.  Then in the timer ISR I make the cpu active after exiting the timer ISR by issuing :

          __bic_SR_register_on_exit(LPM0_bits); // CPU active on reti

    When the main routine is wakened, it sees the flag is set by the timer and does what it needs to do at a normal priority.  After the main routine is finished it goes back to sleep.
    I don't fully understand what all is going on in the timer example I found but I'm sure it does what I want.  The example is msp430x21x2_ta0_22.c
    It is also good to know that no other interrupts will occur once an interrupt is granted until the GIE is set again.
    Thanks for your help.

  • 0 in reply to Jim Young
    Guru 227245 points

    Jim Young said:
    I set a flag in the timer ISR indicating to the main routine that I need to do something.  Then in the timer ISR I make the cpu active after exiting the timer ISR

    Yep, that's the usual/recommended way to do it.
    Jim Young said:
    It is also good to know that no other interrupts will occur once an interrupt is granted until the GIE is set again.
    It is a vital thing. Except for a few cases where entering the ISR implicitely clears the IFG bit (e.g. in timer CCR0 ISR), the interrupt is still pending until the IFG bit is cleared. If you set GIE before you cleared the IFG bit that cause the current interrupt, the CPU would interrupt the ISR immediately just to call it again to serve the still pending interrupt. And again. And again. (never comming to the point where the interrupt event is really handled).
    This is important even if not manually setting GIE inside the ISR: the moment the ISR returns, GIE is set again (restored from stack), and if the IFG bti is still set, it will immediately call the ISR again. Only that this time the ISR had been finished before, so the stack doesn't overflow. Still an eternal loop, only interrupted by higher priority interrupts (between two ISR calls). And main would be virtually frozen.

**Attention** This is a public forum