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PWM inversion problem

Michael Dalton
Intellectual 650 points

Hello,

I have recently made a Boost converter that is controlled with the MSP430. I have got the boost converter to run as a regular boost converter well, but want to change the topology to synchronous by replacing the diode in the circuit to a PMOS (high side) switch.

The first waveform in the picture shows the unloaded output from the MSP430, complimented PWM with deadtime to avoid shoot through in the converter. I needed to invert the PMOS drive so used a simple logic inverter using a NPN transistor.

The second waveform shows the output form the MSP430 to the input of the MOS drive circuits and the third the outputs from the MOS drive circuits.

I am having trouble with the logic inverter as the falling edge of the input signal rolls off instead of falling quickly.

The last waveform is what would be the best outcome, but i can not get it to work.

Can someone help me with a suggestion of how to remedy this problem or how to invert a PWM signal with no deterioration of the signal (except for the inversion of course :).

Thanks

Michael Dalton

 

  • 0
    Guru 58965 points

    Maybe you saturated the NPN and it would not turn off quickly. Try add a resistor between the MSP430 and the base of this transistor.

     

  • 0 in reply to old_cow_yellow
    Intellectual 650 points

    Hey old_cow_yellow,

    I added a 1000k ohm resistor from the MSP430 to the base but the transistor but is still isn't turning off hard.

    It still turns on fine though.

    I also tried a 10KOhm from the base drive line to ground but that yielded no change either.

    Maybe i could increase the collector resistor.

    Will have to do when i get back to the desk though.

     

    Regards

     

    Michael Dalton

  • 0
    Guru 227245 points

    The fact that the output voltage on the second diagram is breakign down indicates that you are shortcutting the MSP output port and most likely are overloading the transistor base.

    For the PMos, you need a resistor to the PMOS source and a transistor/switch to GND. The pullup resistor needs to be small enough so it will 'refill' the PMOS gate fast. The ideal balance is a pullup current tha tis twice the pulldown (transistor) current for a symmetrical loading and unoalding of the PMOS gate, but may be adjusted eithe rway to fir the relation of PMOS gate threshold voltage and PMOS source voltage etc.

    The slow falling of the MSP output signal shws that there is still current flowing into the transistor base when the output tries to shut off. This is partly a sifde-effect of drifing the output to its current limit. A base resistor helps. However, the slow rising of the driver output means that not only the transistor is still driving a bit, but also that the pullup resistor is not strong enough to pull the pmos gate high again.
    power most transistorsoften have a really large gate capacitance, so for fast switching, a significant current must flow. In both directions, so not only throught he transistor but also through the pullup resistor. 1K is probably too large for your setup.

  • 0 in reply to Jens-Michael Gross
    Intellectual 650 points

    Jens-Michael Gross said:

    For the PMos, you need a resistor to the PMOS source and a transistor/switch to GND. The pullup resistor needs to be small enough so it will 'refill' the PMOS gate fast. The ideal balance is a pullup current tha tis twice the pulldown (transistor) current for a symmetrical loading and unoalding of the PMOS gate, but may be adjusted eithe rway to fir the relation of PMOS gate threshold voltage and PMOS source voltage etc.

    Is this what you meant with the placement of the resistors?

     

    Jens-Michael Gross said:


    power most transistorsoften have a really large gate capacitance, so for fast switching, a significant current must flow. In both directions, so not only throught he transistor but also through the pullup resistor. 1K is probably too large for your setup.

    Do you mean the collector resistor or the MOS source resistor?

    Also. Should i put a zenner to GND on the output of the MSP to the base of the NPN

    Thanks

     

    Michael Dalton

     

     

  • 0
    Guru 58965 points

    Another way to do it. Modify the MSP430 code to invert the second PWM output. Use a emitter follower (which does not invert) to drive your PMOS.

  • 0 in reply to old_cow_yellow
    Intellectual 650 points

    old_cow_yellow said:

    Another way to do it. Modify the MSP430 code to invert the second PWM output. Use a emitter follower (which does not invert) to drive your PMOS.

    That is probably easier. I could use the same totem pole circuit to drive the PMOS as i do for the nMOS.

     

    P.S. Have they found a replacement for you as moderator of the MSP430 community yet??

  • 0 in reply to Michael Dalton
    Intellectual 650 points

    old_cow_yellow said:

    Another way to do it. Modify the MSP430 code to invert the second PWM output. Use a emitter follower (which does not invert) to drive your PMOS.

    Yeah that worked. Just changed output mode for CCR2 to OUTMOD6 (CCR1 is the same).

    Should have though about that before (face palm).

     

  • 0 in reply to Michael Dalton
    Guru 227245 points

    Michael Dalton said:
    Do you mean the collector resistor or the MOS source resistor?

    Actually I thought the collector resistor WAS the MOS soure resistor.
    The purpose of the transistor was to pull the MOS gate below teh MSO source level, and the only purpose of a resistor here is to pull the gate back to MOS source level if the transistor stops sinking it. Like a spring on a mechanical door-closer that closes the door when you release the handle. The closing speed depends on the strength of the spring and the door mechanics (gate capacity) , while the stronger the spring, the more power you need to open the door.

    Michael Dalton said:
    Also. Should i put a zenner to GND on the output of the MSP to the base of the NPN

    No need to. The MSP port pins have CLAMP diodes which sink any excess voltage to VCC or GND, up to 2mA. There shouldn't be a collector-base current that large, unless the MOS source voltage exceeds what the transistor can bear. Also, the transistor base/emitter works like a zener diode too (it is already sinking the MSP output current down to a few 100mV in your original setup)

    However, you already got a solution that works. Fine.

  • 0 in reply to Jens-Michael Gross
    Intellectual 650 points

    Jens-Michael Gross said:

    Actually I thought the collector resistor WAS the MOS soure resistor.

    No, i had just used a simple logic inverting circuit and fed that to the gate of the PMOSFET. I didn't think to attach it to the source though.

    Jens-Michael Gross said:

    The purpose of the transistor was to pull the MOS gate below teh MSO source level, and the only purpose of a resistor here is to pull the gate back to MOS source level if the transistor stops sinking it. Like a spring on a mechanical door-closer that closes the door when you release the handle. The closing speed depends on the strength of the spring and the door mechanics (gate capacity) , while the stronger the spring, the more power you need to open the door.

    That's a good explanation. So it's like the pull down resitor when driving a NMOS.

    Jens-Michael Gross said:

    However, you already got a solution that works. Fine.

    Yeah, but thanks for the reply anyway :)

     

  • 0 in reply to Michael Dalton
    Guru 227245 points

    Michael Dalton said:
    No, i had just used a simple logic inverting circuit and fed that to the gate of the PMOSFET. I didn't think to attach it to the source though.

    So it was pure coincidence that the PMOS was closing at all. PMOS gate needs to be on PMOS source level (or typically up to 1-2V below, the 'threshold' voltage) to 'open' the PMOS.

    Michael Dalton said:
    So it's like the pull down resitor when driving a NMOS.

    Yes. NMOS and PMOS are mirrored.
    The practical difference is that in NMOS, you usually have the transistor drain on GND, so the gate requires a voltage of 0 to ~3-5V.

    For the PMOS, it usually 'hangs' on the controlled devices supply voltage, so you have to deal with 'VCC' and 'VCC- ~3-5V'. And VCC usually is much higher than normal logic voltage in most applications with a high-side PMOS driver.

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